From f86c1ff7b39146f23cd1959bcc63dcb3b0b27125 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Sun, 23 Oct 2022 22:27:06 +0000 Subject: Fix for <> to BlackBox.IO with Compatibility Bundles (#2801) (#2803) MonoConnect.traceFlow now properly handles coerced directions. Also minor improvement to getClassName especially useful in test case printf debugging. (cherry picked from commit 3aba755bdcf996c0fbd846d13268fd6641b29e96) Co-authored-by: Megan Wachs --- .../CompatibilityInteroperabilitySpec.scala | 155 +++++++++++++++++++++ 1 file changed, 155 insertions(+) (limited to 'src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala') diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala index 1e199297..e2fb2179 100644 --- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala @@ -3,6 +3,7 @@ package chiselTests import scala.collection.immutable.ListMap +import chisel3.stage.ChiselStage.emitChirrtl // Keep Chisel._ separate from chisel3._ below object CompatibilityComponents { @@ -390,4 +391,158 @@ class CompatibilityInteroperabilitySpec extends ChiselFlatSpec { compile(new Top(true)) compile(new Top(false)) } + + "A BlackBox with Chisel._ fields in its IO" should "bulk connect in import chisel3._ code correctly" in { + object Compat { + import Chisel._ + class LegacyChiselIO extends Bundle { + val foo = Output(Bool()) + val bar = Output(Bool()) + } + } + object Chisel3 { + import chisel3._ + import chisel3.util.Valid + + class FooModuleIO extends Bundle { + val quz = Input(new QuzIO) + val foo = Output(Bool()) + val bar = Input(Bool()) + } + class QuzIO extends Bundle { + val q = Flipped(Valid(new Compat.LegacyChiselIO)) + } + class FooModule extends Module { + val io = IO(new FooModuleIO) + io <> DontCare + } + class FooMirrorBlackBox extends BlackBox { + val io = IO(Flipped(new FooModuleIO)) + } + class Top extends Module { + val foo = Module(new FooModule) + val mirror = Module(new FooMirrorBlackBox) + foo.io <> mirror.io + } + } + val chirrtl = emitChirrtl(new Chisel3.Top) + chirrtl should include("foo.io.bar <= mirror.bar") + chirrtl should include("mirror.foo <= foo.io.foo") + chirrtl should include("foo.io.quz.q.bits <- mirror.quz.q.bits") + chirrtl should include("foo.io.quz.q.valid <= mirror.quz.q.valid") + } + + "A chisel3.Bundle bulk connected to a Chisel Bundle in either direction" should "work even with mismatched fields" in { + object Compat { + import Chisel._ + class FooBundle extends Bundle { + val foo = UInt(width = 8) + } + } + object Chisel3 { + import chisel3._ + class BarBundle extends Bundle { + val bar = UInt(8.W) + } + class MyModule(swap: Boolean) extends Module { + val in = IO(Input(if (swap) new Compat.FooBundle else new BarBundle)) + val out = IO(Output(if (swap) new BarBundle else new Compat.FooBundle)) + out <> DontCare + out <> in + } + } + val chirrtl0 = emitChirrtl(new Chisel3.MyModule(true)) + chirrtl0 shouldNot include("<=") + chirrtl0 should include("out <- in") + val chirrtl1 = emitChirrtl(new Chisel3.MyModule(true)) + chirrtl1 shouldNot include("<=") + chirrtl1 should include("out <- in") + } + + it should "work with missing fields in the Chisel._" in { + object Compat { + import Chisel._ + class FooBundle extends Bundle { + val foo = UInt(width = 8) + } + } + object Chisel3 { + import chisel3._ + class FooBarBundle extends Bundle { + val foo = UInt(8.W) + val bar = UInt(8.W) + } + + class MyModule(swap: Boolean) extends Module { + val in = IO(Input(if (swap) new Compat.FooBundle else new FooBarBundle)) + val out = IO(Output(if (swap) new FooBarBundle else new Compat.FooBundle)) + out <> DontCare + out <> in + } + } + val chirrtl0 = emitChirrtl(new Chisel3.MyModule(true)) + chirrtl0 shouldNot include("<=") + chirrtl0 should include("out <- in") + val chirrtl1 = emitChirrtl(new Chisel3.MyModule(true)) + chirrtl1 shouldNot include("<=") + chirrtl1 should include("out <- in") + } + + it should "work with missing fields in the chisel3._" in { + object Compat { + import Chisel._ + class FooBundle extends Bundle { + val foo = UInt(width = 8) + } + } + object Chisel3 { + import chisel3._ + class FooBarBundle extends Bundle { + val foo = UInt(8.W) + val bar = UInt(8.W) + } + + class MyModule(swap: Boolean) extends Module { + val in = IO(Input(if (swap) new Compat.FooBundle else new FooBarBundle)) + val out = IO(Output(if (swap) new FooBarBundle else new Compat.FooBundle)) + out <> DontCare + out <> in + } + } + val chirrtl0 = emitChirrtl(new Chisel3.MyModule(true)) + chirrtl0 shouldNot include("<=") + chirrtl0 should include("out <- in") + val chirrtl1 = emitChirrtl(new Chisel3.MyModule(true)) + chirrtl1 shouldNot include("<=") + chirrtl1 should include("out <- in") + } + + it should "emit FIRRTL connects if possible" in { + object Compat { + import Chisel._ + class FooBarBundle extends Bundle { + val foo = UInt(8.W) + val bar = Flipped(UInt(8.W)) + } + } + object Chisel3 { + import chisel3._ + class FooBarBundle extends Bundle { + val foo = Output(UInt(8.W)) + val bar = Input(UInt(8.W)) + } + class MyModule(swap: Boolean) extends Module { + val in = IO(Flipped((if (swap) new Compat.FooBarBundle else new FooBarBundle))) + val out = IO(if (swap) new FooBarBundle else new Compat.FooBarBundle) + out <> DontCare + out <> in + } + } + val chirrtl0 = emitChirrtl(new Chisel3.MyModule(true)) + chirrtl0 should include("out <= in") + chirrtl0 shouldNot include("out <- in") + val chirrtl1 = emitChirrtl(new Chisel3.MyModule(true)) + chirrtl1 should include("out <= in") + chirrtl1 shouldNot include("out <- in") + } } -- cgit v1.2.3