From e27657118ff5915b96f8e3a467d464245fe09769 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 20 Dec 2017 15:54:25 -0800
Subject: Add compileOptions to Module.apply, use for invalidating submod ports
 (#747)

Fixes #746
Also add test for https://github.com/freechipsproject/firrtl/issues/705
---
 .../CompatibilityInteroperabilitySpec.scala        | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala')

diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index c0538123..457f26de 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -217,5 +217,27 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
       stop()
     })
   }
+
+  "An instance of a chisel3.Module inside a Chisel.Module" should "have its inputs invalidated" in {
+    compile {
+      import Chisel._
+      new Module {
+        val io = new Bundle {
+          val in = UInt(INPUT, width = 32)
+          val cond = Bool(INPUT)
+          val out = UInt(OUTPUT, width = 32)
+        }
+        val children = Seq(Module(new PassthroughModule),
+                           Module(new PassthroughMultiIOModule),
+                           Module(new PassthroughRawModule))
+        io.out := children.map(_.io.out).reduce(_ + _)
+        children.foreach { child =>
+          when (io.cond) {
+            child.io.in := io.in
+          }
+        }
+      }
+    }
+  }
 }
 
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