From 16c0b53e04f3a78ddaaa382936cd660523a57199 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Thu, 8 Jul 2021 15:30:28 -0700 Subject: Fix chisel3 <> for Bundles that contain compatibility Bundles (#2023) BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a Bundle defined in `import Chisel._`. Because chisel3 <> is commutative it needs to be mindful of flippedness when emitting a FIRRTL <- (which is *not* commutative).--- .../CompatibilityInteroperabilitySpec.scala | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala') diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala index cfcc4608..8e9f9e7e 100644 --- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala @@ -289,5 +289,43 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec { } } } + + "A chisel3 Bundle that instantiates a Chisel Bundle" should "bulk connect correctly" in { + compile { + object Compat { + import Chisel._ + class Foo extends Bundle { + val a = Input(UInt(8.W)) + val b = Output(UInt(8.W)) + } + } + import chisel3._ + import Compat._ + class Bar extends Bundle { + val foo1 = new Foo + val foo2 = Flipped(new Foo) + } + // Check every connection both ways to see that chisel3 <>'s commutativity holds + class Child extends RawModule { + val deq = IO(new Bar) + val enq = IO(Flipped(new Bar)) + enq <> deq + deq <> enq + } + new RawModule { + val deq = IO(new Bar) + val enq = IO(Flipped(new Bar)) + // Also important to check connections to child ports + val c1 = Module(new Child) + val c2 = Module(new Child) + c1.enq <> enq + enq <> c1.enq + c2.enq <> c1.deq + c1.deq <> c2.enq + deq <> c2.deq + c2.deq <> deq + } + } + } } -- cgit v1.2.3 From 5183ef888274c1d9cc2e22aef95c0e90d86e5122 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Fri, 9 Jul 2021 14:29:45 -0700 Subject: Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031) PR #2023 fixed a composition issue for chisel3 biconnects delegating to FIRRTL partial connect when compatibility mode Bundles are elements of chisel3 Bundles. It missed an important case though that caused previously working code to break. The bug is fixed by doing the automatic flipping for compatibility mode Bundles that have "Input" as a direction in addition to those that are "Flipped".--- .../scala/chiselTests/CompatibilityInteroperabilitySpec.scala | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala') diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala index 8e9f9e7e..28b8bc80 100644 --- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala @@ -294,16 +294,21 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec { compile { object Compat { import Chisel._ - class Foo extends Bundle { + class BiDir extends Bundle { val a = Input(UInt(8.W)) val b = Output(UInt(8.W)) } + class Struct extends Bundle { + val a = UInt(8.W) + } } import chisel3._ import Compat._ class Bar extends Bundle { - val foo1 = new Foo - val foo2 = Flipped(new Foo) + val bidir1 = new BiDir + val bidir2 = Flipped(new BiDir) + val struct1 = Output(new Struct) + val struct2 = Input(new Struct) } // Check every connection both ways to see that chisel3 <>'s commutativity holds class Child extends RawModule { -- cgit v1.2.3 From 7fb2c1ebc23ca07e5de6416a284e1be1b62a48ac Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Mon, 30 Aug 2021 18:56:33 -0700 Subject: Fix chisel3 <> for compatibility Bundles (Take 3) (#2093) Previous incomplete fixes in #2023 and #2031. The legality of a FIRRTL connection is determined by type and flow. Chisel does not have access to true flow information. Previous fix attempts tried to use ActualDirection as a stand-in for flow, but it is incorrect in many cases. This new approach checks the flows of the lvalue and rvalues in the connect and flips the connection if either the lvalue cannot be a sink or the rvalue cannot be a source.--- .../CompatibilityInteroperabilitySpec.scala | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala') diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala index 28b8bc80..1795cc1f 100644 --- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala @@ -332,5 +332,32 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec { } } } + + "A unidirectional but flipped Bundle" should "bulk connect in import chisel3._ code correctly" in { + object Compat { + import Chisel._ + class MyBundle(extraFlip: Boolean) extends Bundle { + private def maybeFlip[T <: Data](t: T): T = if (extraFlip) t.flip else t + val foo = maybeFlip(new Bundle { + val bar = UInt(INPUT, width = 8) + }) + override def cloneType = (new MyBundle(extraFlip)).asInstanceOf[this.type] + } + } + import chisel3._ + import Compat._ + class Top(extraFlip: Boolean) extends RawModule { + val port = IO(new MyBundle(extraFlip)) + val wire = Wire(new MyBundle(extraFlip)) + port <> DontCare + wire <> DontCare + port <> wire + wire <> port + port.foo <> wire.foo + wire.foo <> port.foo + } + compile(new Top(true)) + compile(new Top(false)) + } } -- cgit v1.2.3