From 24dddea6dccea5a570cece78324a5db624c7303a Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 13 Aug 2019 15:06:58 +0530
Subject: Add support for asynchronous reset (#1011)

Adds new AsyncReset and "abstract" Reset types. Reset is inferred
in FIRRTL to be either AsyncReset or Bool. The "reset type" of a
register is set by the type of its reset signal:

  val asyncReset: AsyncReset = IO(Input(AsyncReset()))
  val syncReset: Bool = IO(Input(Bool()))
  val abstractReset: Reset = IO(Input(Reset()))

  val asyncReg = withReset(asyncReset) { RegInit(0.U) }
  val syncReg = withReset(syncReset) { RegInit(0.U) }
  val inferredReg = withReset(abstractReset) { RegInit(0.U) }

AsyncReset can be cast to and from Bool. Whereas synchronous reset is
equivalent to a mux in front of a flip-flop and thus can be driven by
logic, asynchronous reset requires that the reset value is a constant.
This is checked in FIRRTL.

Inference of the concrete type of a Reset occurs based on the type the
Reset's drivers. This inference is very simple, it is simple forward propagation
of the type, but it allows for writing blocks and modules that are agnostic
to the reset type. In particular, the implicit `reset` value in MultiIOModule
and thus Module is now concretely an instance of Reset and thus will be
inferred in FIRRTL.---
 src/test/scala/chiselTests/CloneModuleSpec.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test/scala/chiselTests/CloneModuleSpec.scala')

diff --git a/src/test/scala/chiselTests/CloneModuleSpec.scala b/src/test/scala/chiselTests/CloneModuleSpec.scala
index 59ba2eb5..ca8bd007 100644
--- a/src/test/scala/chiselTests/CloneModuleSpec.scala
+++ b/src/test/scala/chiselTests/CloneModuleSpec.scala
@@ -9,7 +9,7 @@ import chisel3.testers.BasicTester
 
 class MultiIOQueue[T <: Data](gen: T, val entries: Int) extends MultiIOModule {
   val clk = IO(Input(Clock()))
-  val rst = IO(Input(Bool()))
+  val rst = IO(Input(Reset()))
   val enq = IO(Flipped(EnqIO(gen)))
   val deq = IO(Flipped(DeqIO(gen)))
   val count = IO(Output(UInt(log2Ceil(entries + 1).W)))
@@ -28,7 +28,7 @@ class QueueClone(multiIO: Boolean = false) extends Module {
     q1.rst := reset
     q1.enq <> io.enq
     q2_io("clk").asInstanceOf[Clock] := clock
-    q2_io("rst").asInstanceOf[Bool] := reset
+    q2_io("rst").asInstanceOf[Reset] := reset
     q2_io("enq").asInstanceOf[q1.enq.type] <> q1.deq
     io.deq <> q2_io("deq").asInstanceOf[q1.deq.type]
     io.count := q1.count + q2_io("count").asInstanceOf[q1.count.type]
-- 
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