From 53b620478ddab1faa96512e473fa198f7f1fcf50 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Tue, 9 Feb 2021 17:12:37 -0800 Subject: Add no-plugin-tests for testing Chisel without the compiler plugin This is a new SBT build unit that symlinks in some files from the normal chisel project tests, but builds them without the compiler plugin. --- .../chiselTests/ChiselTestUtilitiesSpec.scala | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala (limited to 'src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala') diff --git a/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala b/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala new file mode 100644 index 00000000..6d3d526c --- /dev/null +++ b/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: Apache-2.0 + +package chiselTests + +import chisel3._ +import org.scalatest.exceptions.TestFailedException + +class ChiselTestUtilitiesSpec extends ChiselFlatSpec { + // Who tests the testers? + "assertKnownWidth" should "error when the expected width is wrong" in { + val caught = intercept[ChiselException] { + assertKnownWidth(7) { + Wire(UInt(8.W)) + } + } + assert(caught.getCause.isInstanceOf[TestFailedException]) + } + + it should "error when the width is unknown" in { + a [ChiselException] shouldBe thrownBy { + assertKnownWidth(7) { + Wire(UInt()) + } + } + } + + it should "work if the width is correct" in { + assertKnownWidth(8) { + Wire(UInt(8.W)) + } + } + + "assertInferredWidth" should "error if the width is known" in { + val caught = intercept[ChiselException] { + assertInferredWidth(8) { + Wire(UInt(8.W)) + } + } + assert(caught.getCause.isInstanceOf[TestFailedException]) + } + + it should "error if the expected width is wrong" in { + a [TestFailedException] shouldBe thrownBy { + assertInferredWidth(8) { + val w = Wire(UInt()) + w := 2.U(2.W) + w + } + } + } + + it should "pass if the width is correct" in { + assertInferredWidth(4) { + val w = Wire(UInt()) + w := 2.U(4.W) + w + } + } +} + -- cgit v1.2.3