From f8408623e13149ccd4bfae443d916eeb9c5a2146 Mon Sep 17 00:00:00 2001
From: Jack
Date: Mon, 30 Jan 2017 22:34:25 -0800
Subject: Add compile [to Verilog] to ChiselRunners

---
 src/test/scala/chiselTests/ChiselSpec.scala | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/ChiselSpec.scala')

diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 7b915c09..4588abe1 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -8,6 +8,12 @@ import org.scalatest.prop._
 import org.scalacheck._
 import chisel3._
 import chisel3.testers._
+import firrtl.{
+  ExecutionOptionsManager,
+  HasFirrtlOptions,
+  FirrtlExecutionSuccess,
+  FirrtlExecutionFailure
+}
 
 /** Common utility functions for Chisel unit tests. */
 trait ChiselRunners extends Assertions {
@@ -21,7 +27,20 @@ trait ChiselRunners extends Assertions {
     assert(!runTester(t, additionalVResources))
   }
   def elaborate(t: => Module): Unit = Driver.elaborate(() => t)
-
+  /** Compiles a Chisel Module to Verilog */
+  def compile(t: => Module): String = {
+    val manager = new ExecutionOptionsManager("compile") with HasFirrtlOptions
+                                                         with HasChiselExecutionOptions
+    Driver.execute(manager, () => t) match {
+      case ChiselExecutionSuccess(_, _, Some(firrtlExecRes)) =>
+        firrtlExecRes match {
+          case FirrtlExecutionSuccess(_, verilog) => verilog
+          case FirrtlExecutionFailure(msg) => fail(msg)
+        }
+      case ChiselExecutionSuccess(_, _, None) => fail() // This shouldn't happen
+      case ChiselExecutionFailure(msg) => fail(msg)
+    }
+  }
 }
 
 /** Spec base class for BDD-style testers. */
-- 
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