From aaf963f95bf1f4e9f3e5a8225925b4df7d01e795 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Thu, 18 Jul 2019 22:39:27 -0700
Subject: Support Analog DontCare bulk-connect (#1056)

Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.---
 src/test/scala/chiselTests/ChiselSpec.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/ChiselSpec.scala')

diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 0a0eb3f0..5973cb63 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -147,7 +147,7 @@ class ChiselTestUtilitiesSpec extends ChiselFlatSpec {
 class ChiselPropSpec extends PropSpec with ChiselRunners with PropertyChecks with Matchers {
 
   // Constrain the default number of instances generated for every use of forAll.
-  implicit override val generatorDrivenConfig =
+  implicit override val generatorDrivenConfig: PropertyCheckConfiguration =
     PropertyCheckConfiguration(minSuccessful = 8, minSize = 1, sizeRange = 3)
 
   // Generator for small positive integers.
-- 
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