From ad96b03f84d0182f5e74f11117331d69752ea0a0 Mon Sep 17 00:00:00 2001
From: Henry Cook
Date: Thu, 13 Aug 2015 15:47:02 -0700
Subject: testing improvements

---
 src/test/scala/chiselTests/BundleWire.scala | 39 +++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 src/test/scala/chiselTests/BundleWire.scala

(limited to 'src/test/scala/chiselTests/BundleWire.scala')

diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
new file mode 100644
index 00000000..99455608
--- /dev/null
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -0,0 +1,39 @@
+package chiselTests
+import Chisel._
+import org.scalatest._
+import org.scalatest.prop._
+import Chisel.testers.BasicTester
+
+class Coord extends Bundle {
+  val x = UInt(width = 32)
+  val y = UInt(width = 32)
+}
+
+class BundleWire(n: Int) extends Module {
+  val io = new Bundle {
+    val in   = (new Coord).asInput
+    val outs = Vec(new Coord, n).asOutput
+  }
+  val coords = Wire(Vec(new Coord, n))
+  for (i <- 0 until n) {
+    coords(i)  := io.in
+    io.outs(i) := coords(i)
+  }
+}
+
+class BundleWireSpec extends ChiselPropSpec {
+
+  class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
+    val dut = Module(new BundleWire(n))
+    io.done := Bool(true)
+    dut.io.in.x := UInt(x)
+    dut.io.in.y := UInt(y)
+    io.error := dut.io.outs.map(o => o.x != UInt(x) || o.y != UInt(y)).foldLeft(UInt(0))(_##_)
+  }
+
+  property("All vec elems should match the inputs") {
+    forAll(vecSizes, safeUInts, safeUInts) { (n: Int, x: Int, y: Int) =>
+      assert(execute{ new BundleWireTester(n, x, y) })
+    }
+  }
+}
-- 
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