From 0a17d89fe76c11efadc3d0f90dc1d93a690d861a Mon Sep 17 00:00:00 2001
From: chick
Date: Tue, 17 Dec 2019 13:26:08 -0800
Subject: This adds a mechanism for the unittests to be run with the
 TreadleBackend This mechanism is not enabled and should not change the
 behavior of existing tests A following PR will deliver a switch that will
 allow changing the backend. The reasons for this PR - Treadle tests run much
 faster, enabling quicker debugging and CI cycles - This will help ensure
 fidelity of Treadle to the Verilator backend

A few tests are marked as verilator only due to black box limitations

Change treadle to a direct dependency

I tried to make it a test only dependency but the TesterDriver sits in src/main requiring that
regular compile have access to treadle

Oops, made treadle the default

A number of changes in response to @ducky64 review
- made backend check clearer and add error handling for multiple backends specified
- Fixed duplicate TargetDirAnnotation uses in Treadle backend
- Cleaned up BlackBox test formatting
- Undid unnecessary debugging changes from Counter
- Undid .gitignore change, that should be on another PR

A number of changes in response to @ducky64 review
- Undid debugging changes made to BitWiseOps
---
 src/test/scala/chiselTests/BoringUtilsSpec.scala | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

(limited to 'src/test/scala/chiselTests/BoringUtilsSpec.scala')

diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala
index 997466c0..ffc10c88 100644
--- a/src/test/scala/chiselTests/BoringUtilsSpec.scala
+++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util.Counter
-import chisel3.testers.BasicTester
+import chisel3.testers.{BasicTester, TesterDriver}
 import chisel3.experimental.{BaseModule, ChiselAnnotation, RunFirrtlTransform}
 import chisel3.util.experimental.BoringUtils
 
@@ -49,7 +49,8 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
   behavior of "BoringUtils.{addSink, addSource}"
 
   it should "connect two wires within a module" in {
-    runTester(new ShouldntAssertTester { val dut = Module(new BoringInverter) } ) should be (true)
+    runTester(new ShouldntAssertTester { val dut = Module(new BoringInverter) },
+      annotations = TesterDriver.verilatorOnly) should be (true)
   }
 
   trait WireX { this: BaseModule =>
@@ -103,11 +104,12 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
   behavior of "BoringUtils.bore"
 
   it should "connect across modules using BoringUtils.bore" in {
-    runTester(new TopTester) should be (true)
+    runTester(new TopTester, annotations = TesterDriver.verilatorOnly) should be (true)
   }
 
   it should "throw an exception if NoDedupAnnotations are removed" in {
-    intercept[WiringException] { runTester(new TopTester with FailViaDedup) }
+    intercept[WiringException] { runTester(new TopTester with FailViaDedup,
+      annotations = Seq(TesterDriver.VerilatorBackend)) }
       .getMessage should startWith ("Unable to determine source mapping for sink")
   }
 
@@ -125,7 +127,7 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
   }
 
   it should "work for an internal (same module) BoringUtils.bore" in {
-    runTester(new InternalBoreTester) should be (true)
+    runTester(new InternalBoreTester, annotations = TesterDriver.verilatorOnly) should be (true)
   }
 
 }
-- 
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