From 5509cdd4c8332c53151e10ba5bdbe0684af1c05b Mon Sep 17 00:00:00 2001
From: Martin Schoeberl
Date: Fri, 25 Jan 2019 23:24:01 -0800
Subject: WireDefault instead of WireInit, keep WireInit around (#986)

---
 src/test/scala/chiselTests/AnalogSpec.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/AnalogSpec.scala')

diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala
index d4769f41..c5e9ed02 100644
--- a/src/test/scala/chiselTests/AnalogSpec.scala
+++ b/src/test/scala/chiselTests/AnalogSpec.scala
@@ -118,7 +118,7 @@ class AnalogSpec extends ChiselFlatSpec {
   it should "NOT be connectable to UInts" in {
     a [Exception] should be thrownBy {
       runTester { new BasicTester {
-        val uint = WireInit(0.U(32.W))
+        val uint = WireDefault(0.U(32.W))
         val sint = Wire(Analog(32.W))
         sint := uint
       }}
-- 
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