From 2ae50411cbc5e2cd5fdc9ca4069b9c5f64919bc4 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 11 May 2015 13:02:03 -0700
Subject: Incorporate chisel3-tests; update Makefile.

---
 src/test/scala/ChiselTests/VecShiftRegister.scala | 28 +++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 src/test/scala/ChiselTests/VecShiftRegister.scala

(limited to 'src/test/scala/ChiselTests/VecShiftRegister.scala')

diff --git a/src/test/scala/ChiselTests/VecShiftRegister.scala b/src/test/scala/ChiselTests/VecShiftRegister.scala
new file mode 100644
index 00000000..7a761801
--- /dev/null
+++ b/src/test/scala/ChiselTests/VecShiftRegister.scala
@@ -0,0 +1,28 @@
+package ChiselTests
+import Chisel._
+
+class VecShiftRegister extends Module {
+  val io = new Bundle {
+    val ins   = Vec(UInt(INPUT, 4), 4)
+    val load  = Bool(INPUT)
+    val shift = Bool(INPUT)
+    val out   = UInt(OUTPUT, 4)
+  }
+  val delays = Reg(Vec(UInt(width = 4), 4))
+  when (io.load) {
+    delays(0) := io.ins(0)
+    delays(1) := io.ins(1)
+    delays(2) := io.ins(2)
+    delays(3) := io.ins(3)
+  } .elsewhen(io.shift) {
+    delays(0) := io.ins(0)
+    delays(1) := delays(0)
+    delays(2) := delays(1)
+    delays(3) := delays(2)
+  }
+  io.out := delays(3)
+}
+
+
+class VecShiftRegisterTester(c: VecShiftRegister) extends Tester(c) {
+}
-- 
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