From 2ae50411cbc5e2cd5fdc9ca4069b9c5f64919bc4 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 11 May 2015 13:02:03 -0700
Subject: Incorporate chisel3-tests; update Makefile.

---
 src/test/scala/ChiselTests/Rom.scala | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 src/test/scala/ChiselTests/Rom.scala

(limited to 'src/test/scala/ChiselTests/Rom.scala')

diff --git a/src/test/scala/ChiselTests/Rom.scala b/src/test/scala/ChiselTests/Rom.scala
new file mode 100644
index 00000000..7c7eb1ac
--- /dev/null
+++ b/src/test/scala/ChiselTests/Rom.scala
@@ -0,0 +1,23 @@
+package ChiselTests
+import Chisel._
+
+class Rom extends Module {
+  val io = new Bundle {
+    val addr = UInt(INPUT,  4)
+    val out  = UInt(OUTPUT, 5)
+  }
+  val r = Vec(Range(0, 1 << 4).map(i => UInt(i * 2, width = 5)))
+  io.out := r(io.addr)
+}
+
+
+class RomTester(c: Rom) extends Tester(c) {
+  val r = Array.tabulate(1 << 4){ i => i * 2}
+  for (i <- 0 until 10) {
+    val a = rnd.nextInt(1 << 4)
+    poke(c.io.addr, a)
+    step(1)
+    expect(c.io.out, r(a))
+  }
+
+}
-- 
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