From 2ae50411cbc5e2cd5fdc9ca4069b9c5f64919bc4 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 11 May 2015 13:02:03 -0700
Subject: Incorporate chisel3-tests; update Makefile.

---
 .../scala/ChiselTests/EnableShiftRegister.scala    | 39 ++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 src/test/scala/ChiselTests/EnableShiftRegister.scala

(limited to 'src/test/scala/ChiselTests/EnableShiftRegister.scala')

diff --git a/src/test/scala/ChiselTests/EnableShiftRegister.scala b/src/test/scala/ChiselTests/EnableShiftRegister.scala
new file mode 100644
index 00000000..49825271
--- /dev/null
+++ b/src/test/scala/ChiselTests/EnableShiftRegister.scala
@@ -0,0 +1,39 @@
+package ChiselTests
+import Chisel._
+
+class EnableShiftRegister extends Module {
+  val io = new Bundle {
+    val in    = UInt(INPUT, 4)
+    val shift = Bool(INPUT)
+    val out   = UInt(OUTPUT, 4)
+  }
+  val r0 = Reg(init = UInt(0, 4))
+  val r1 = Reg(init = UInt(0, 4))
+  val r2 = Reg(init = UInt(0, 4))
+  val r3 = Reg(init = UInt(0, 4))
+  when(io.shift) {
+    r0 := io.in
+    r1 := r0
+    r2 := r1
+    r3 := r2
+  }
+  io.out := r3
+}
+
+class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
+  val reg = Array.fill(4){ 0 }
+  for (t <- 0 until 16) {
+    val in    = rnd.nextInt(16)
+    val shift = rnd.nextInt(2)
+    println("SHIFT " + shift + " IN " + in)
+    poke(c.io.in,    in)
+    poke(c.io.shift, shift)
+    step(1)
+    if (shift == 1) {
+      for (i <- 3 to 1 by -1)
+        reg(i) = reg(i-1)
+      reg(0) = in
+    }
+    expect(c.io.out, reg(3))
+  }
+}
-- 
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