From 8baa2ab806be1aa85a7a1da7b348726da1bd1d19 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 11 May 2017 15:07:30 -0700
Subject: Scope resources - move them down into chisel3 directory - fixes #549
 (#610)

---
 src/test/resources/AnalogBlackBox.v                | 27 ---------
 src/test/resources/BlackBoxTest.v                  | 67 ----------------------
 src/test/resources/VerilogVendingMachine.v         | 44 --------------
 src/test/resources/chisel3/AnalogBlackBox.v        | 27 +++++++++
 src/test/resources/chisel3/BlackBoxTest.v          | 67 ++++++++++++++++++++++
 src/test/resources/chisel3/VerilogVendingMachine.v | 44 ++++++++++++++
 6 files changed, 138 insertions(+), 138 deletions(-)
 delete mode 100644 src/test/resources/AnalogBlackBox.v
 delete mode 100644 src/test/resources/BlackBoxTest.v
 delete mode 100644 src/test/resources/VerilogVendingMachine.v
 create mode 100644 src/test/resources/chisel3/AnalogBlackBox.v
 create mode 100644 src/test/resources/chisel3/BlackBoxTest.v
 create mode 100644 src/test/resources/chisel3/VerilogVendingMachine.v

(limited to 'src/test/resources')

diff --git a/src/test/resources/AnalogBlackBox.v b/src/test/resources/AnalogBlackBox.v
deleted file mode 100644
index 79e74a13..00000000
--- a/src/test/resources/AnalogBlackBox.v
+++ /dev/null
@@ -1,27 +0,0 @@
-
-module AnalogReaderBlackBox(
-  inout [31:0] bus,
-  output [31:0] out
-);
-  assign bus = 32'dz;
-  assign out = bus;
-endmodule
-
-module AnalogWriterBlackBox(
-  inout [31:0] bus,
-  input [31:0] in
-);
-  assign bus = in;
-endmodule
-
-module AnalogBlackBox #(
-  parameter index=0
-) (
-  inout [31:0] bus,
-  input port_0_in_valid,
-  input [31:0] port_0_in_bits,
-  output [31:0] port_0_out
-);
-  assign port_0_out = bus;
-  assign bus = (port_0_in_valid)? port_0_in_bits + index : 32'dZ;
-endmodule
diff --git a/src/test/resources/BlackBoxTest.v b/src/test/resources/BlackBoxTest.v
deleted file mode 100644
index f88fb4ee..00000000
--- a/src/test/resources/BlackBoxTest.v
+++ /dev/null
@@ -1,67 +0,0 @@
-module BlackBoxInverter(
-    input  [0:0] in,
-    output [0:0] out
-);
-  assign out = !in;
-endmodule
-
-module BlackBoxPassthrough(
-    input  [0:0] in,
-    output [0:0] out
-);
-  assign out = in;
-endmodule
-
-module BlackBoxMinus(
-    input  [15:0] in1,
-    input  [15:0] in2,
-    output [15:0] out
-);
-  assign out = in1 + in2;
-endmodule
-
-module BlackBoxRegister(
-    input  [0:0] clock,
-    input  [0:0] in,
-    output [0:0] out
-);
-  reg [0:0] register;
-  always @(posedge clock) begin
-    register <= in;
-  end
-  assign out = register;
-endmodule
-
-module BlackBoxConstant #(
-  parameter int WIDTH=1,
-  parameter int VALUE=1
-) (
-  output [WIDTH-1:0] out
-);
-  assign out = VALUE;
-endmodule
-
-module BlackBoxStringParam #(
-  parameter string STRING = "zero"
-) (
-  output [31:0] out
-);
-  assign out = (STRING == "one" )? 1 :
-               (STRING == "two" )? 2 : 0;
-endmodule
-
-module BlackBoxRealParam #(
-  parameter real REAL = 0.0
-) (
-  output [63:0] out
-);
-  assign out = $realtobits(REAL);
-endmodule
-
-module BlackBoxTypeParam #(
-  parameter type T = bit
-) (
-  output T out
-);
-  assign out = 32'hdeadbeef;
-endmodule
diff --git a/src/test/resources/VerilogVendingMachine.v b/src/test/resources/VerilogVendingMachine.v
deleted file mode 100644
index c01259bd..00000000
--- a/src/test/resources/VerilogVendingMachine.v
+++ /dev/null
@@ -1,44 +0,0 @@
-// See LICENSE for license details.
-
-// A simple Verilog FSM vending machine implementation
-module VerilogVendingMachine(
-  input clock,
-  input reset,
-  input nickel,
-  input dime,
-  output dispense
-);
-  parameter sIdle = 3'd0, s5 = 3'd1, s10 = 3'd2, s15 = 3'd3, sOk = 3'd4;
-  reg [2:0] state;
-  wire [2:0] next_state;
-
-  assign dispense = (state == sOk) ? 1'd1 : 1'd0;
-
-  always @(*) begin
-    case (state)
-      sIdle: if (nickel) next_state <= s5;
-             else if (dime) next_state <= s10;
-             else next_state <= state;
-      s5: if (nickel) next_state <= s10;
-             else if (dime) next_state <= s15;
-             else next_state <= state;
-      s10: if (nickel) next_state <= s15;
-             else if (dime) next_state <= sOk;
-             else next_state <= state;
-      s15: if (nickel) next_state <= sOk;
-             else if (dime) next_state <= sOk;
-             else next_state <= state;
-      sOk: next_state <= sIdle;
-    endcase
-  end
-
-  // Go to next state
-  always @(posedge clock) begin
-    if (reset) begin
-      state <= sIdle;
-    end else begin
-      state <= next_state;
-    end
-  end
-endmodule
-
diff --git a/src/test/resources/chisel3/AnalogBlackBox.v b/src/test/resources/chisel3/AnalogBlackBox.v
new file mode 100644
index 00000000..79e74a13
--- /dev/null
+++ b/src/test/resources/chisel3/AnalogBlackBox.v
@@ -0,0 +1,27 @@
+
+module AnalogReaderBlackBox(
+  inout [31:0] bus,
+  output [31:0] out
+);
+  assign bus = 32'dz;
+  assign out = bus;
+endmodule
+
+module AnalogWriterBlackBox(
+  inout [31:0] bus,
+  input [31:0] in
+);
+  assign bus = in;
+endmodule
+
+module AnalogBlackBox #(
+  parameter index=0
+) (
+  inout [31:0] bus,
+  input port_0_in_valid,
+  input [31:0] port_0_in_bits,
+  output [31:0] port_0_out
+);
+  assign port_0_out = bus;
+  assign bus = (port_0_in_valid)? port_0_in_bits + index : 32'dZ;
+endmodule
diff --git a/src/test/resources/chisel3/BlackBoxTest.v b/src/test/resources/chisel3/BlackBoxTest.v
new file mode 100644
index 00000000..f88fb4ee
--- /dev/null
+++ b/src/test/resources/chisel3/BlackBoxTest.v
@@ -0,0 +1,67 @@
+module BlackBoxInverter(
+    input  [0:0] in,
+    output [0:0] out
+);
+  assign out = !in;
+endmodule
+
+module BlackBoxPassthrough(
+    input  [0:0] in,
+    output [0:0] out
+);
+  assign out = in;
+endmodule
+
+module BlackBoxMinus(
+    input  [15:0] in1,
+    input  [15:0] in2,
+    output [15:0] out
+);
+  assign out = in1 + in2;
+endmodule
+
+module BlackBoxRegister(
+    input  [0:0] clock,
+    input  [0:0] in,
+    output [0:0] out
+);
+  reg [0:0] register;
+  always @(posedge clock) begin
+    register <= in;
+  end
+  assign out = register;
+endmodule
+
+module BlackBoxConstant #(
+  parameter int WIDTH=1,
+  parameter int VALUE=1
+) (
+  output [WIDTH-1:0] out
+);
+  assign out = VALUE;
+endmodule
+
+module BlackBoxStringParam #(
+  parameter string STRING = "zero"
+) (
+  output [31:0] out
+);
+  assign out = (STRING == "one" )? 1 :
+               (STRING == "two" )? 2 : 0;
+endmodule
+
+module BlackBoxRealParam #(
+  parameter real REAL = 0.0
+) (
+  output [63:0] out
+);
+  assign out = $realtobits(REAL);
+endmodule
+
+module BlackBoxTypeParam #(
+  parameter type T = bit
+) (
+  output T out
+);
+  assign out = 32'hdeadbeef;
+endmodule
diff --git a/src/test/resources/chisel3/VerilogVendingMachine.v b/src/test/resources/chisel3/VerilogVendingMachine.v
new file mode 100644
index 00000000..c01259bd
--- /dev/null
+++ b/src/test/resources/chisel3/VerilogVendingMachine.v
@@ -0,0 +1,44 @@
+// See LICENSE for license details.
+
+// A simple Verilog FSM vending machine implementation
+module VerilogVendingMachine(
+  input clock,
+  input reset,
+  input nickel,
+  input dime,
+  output dispense
+);
+  parameter sIdle = 3'd0, s5 = 3'd1, s10 = 3'd2, s15 = 3'd3, sOk = 3'd4;
+  reg [2:0] state;
+  wire [2:0] next_state;
+
+  assign dispense = (state == sOk) ? 1'd1 : 1'd0;
+
+  always @(*) begin
+    case (state)
+      sIdle: if (nickel) next_state <= s5;
+             else if (dime) next_state <= s10;
+             else next_state <= state;
+      s5: if (nickel) next_state <= s10;
+             else if (dime) next_state <= s15;
+             else next_state <= state;
+      s10: if (nickel) next_state <= s15;
+             else if (dime) next_state <= sOk;
+             else next_state <= state;
+      s15: if (nickel) next_state <= sOk;
+             else if (dime) next_state <= sOk;
+             else next_state <= state;
+      sOk: next_state <= sIdle;
+    endcase
+  end
+
+  // Go to next state
+  always @(posedge clock) begin
+    if (reset) begin
+      state <= sIdle;
+    end else begin
+      state <= next_state;
+    end
+  end
+endmodule
+
-- 
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