From 632a7166ac1935100cb1d61add3b28d1fd4dc8f4 Mon Sep 17 00:00:00 2001
From: Chick Markley
Date: Tue, 31 Jan 2017 09:49:18 -0800
Subject: Move blackbox verilog implementations within reach of verilator
 (#453)

* Move blackbox verilog implementations within reach of verilator
Blackbox implementers can annotate the modules with information on where to get the source verilog
This API is very lightweight, real work is done in firrtl in companion PR
Added some verilog to BlackBoxTest.v resource for testing

* if a file named black_box_verilog_files.f exists add a
-f black_box_verilog_files.f to the verilog to cpp command
---
 src/test/resources/BlackBoxTest.v | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/test/resources')

diff --git a/src/test/resources/BlackBoxTest.v b/src/test/resources/BlackBoxTest.v
index edf321a8..f88fb4ee 100644
--- a/src/test/resources/BlackBoxTest.v
+++ b/src/test/resources/BlackBoxTest.v
@@ -12,6 +12,14 @@ module BlackBoxPassthrough(
   assign out = in;
 endmodule
 
+module BlackBoxMinus(
+    input  [15:0] in1,
+    input  [15:0] in2,
+    output [15:0] out
+);
+  assign out = in1 + in2;
+endmodule
+
 module BlackBoxRegister(
     input  [0:0] clock,
     input  [0:0] in,
-- 
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