From ed894c61474c8bc73761a6c360ef9d14505d853b Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Wed, 18 Aug 2021 03:44:17 +0800
Subject: remove DefRegInit, change DefReg API with option definition. (#1944)

* remove DefRegInit, change DefReg API with option defination.

* add error message

* use Option[RegInitIR].

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 src/main/scala/chisel3/aop/Select.scala              | 1 -
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 3 +--
 2 files changed, 1 insertion(+), 3 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala
index 078422bb..81b4cdab 100644
--- a/src/main/scala/chisel3/aop/Select.scala
+++ b/src/main/scala/chisel3/aop/Select.scala
@@ -101,7 +101,6 @@ object Select {
     check(module)
     module._component.get.asInstanceOf[DefModule].commands.collect {
       case r: DefReg => r.id
-      case r: DefRegInit => r.id
     }
   }
 
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 47849d91..daa83db0 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -66,8 +66,7 @@ private class Emitter(circuit: Circuit) {
     val firrtlLine = e match {
       case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})"
       case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}"
-      case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}"
-      case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"
+      case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}${ if (e.regInit.isDefined) "with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" else ""}"
       case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]"
       case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}"
       case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
-- 
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