From 5ece5aa8ac2716d66a6ed91e38a978049d8bf250 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 20 Jan 2021 13:46:48 -0800 Subject: Rename MultiIOModule to Module --- src/main/scala/chisel3/aop/injecting/InjectingAspect.scala | 4 ++-- src/main/scala/chisel3/util/Decoupled.scala | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/main') diff --git a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala index f9aaceb1..39590b93 100644 --- a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala +++ b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala @@ -2,7 +2,7 @@ package chisel3.aop.injecting -import chisel3.{Module, ModuleAspect, MultiIOModule, RawModule, experimental, withClockAndReset} +import chisel3.{Module, ModuleAspect, RawModule, withClockAndReset} import chisel3.aop._ import chisel3.internal.{Builder, DynamicContext} import chisel3.internal.firrtl.DefModule @@ -63,7 +63,7 @@ abstract class InjectorAspect[T <: RawModule, M <: RawModule]( RunFirrtlTransformAnnotation(new InjectingTransform) +: modules.map { module => val (chiselIR, _) = Builder.build(Module(new ModuleAspect(module) { module match { - case x: MultiIOModule => withClockAndReset(x.clock, x.reset) { injection(module) } + case x: Module => withClockAndReset(x.clock, x.reset) { injection(module) } case x: RawModule => injection(module) } }), dynamicContext) diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index c6459455..032d731d 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle { // Compatibility hack for rocket-chip private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match { - case (true, Some(module: MultiIOModule)) + case (true, Some(module: Module)) if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen) case _ => gen } -- cgit v1.2.3 From 8a73362bb6fe87817a1867cc2482c1841f95c077 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 20 Jan 2021 18:55:16 -0800 Subject: Remove val io Chisel projects no longer need -Xsource:2.11 when compiling with Scala 2.12. Autowrapping of "val io" for compatibility mode Modules is now implemented using reflection instead of calling the virtual method. Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox --- src/main/scala/chisel3/compatibility.scala | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) (limited to 'src/main') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 38ef80ba..7066384b 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -259,16 +259,7 @@ package object Chisel { implicit def resetToBool(reset: Reset): Bool = reset.asBool - import chisel3.experimental.Param - abstract class BlackBox(params: Map[String, Param] = Map.empty[String, Param]) extends chisel3.BlackBox(params) { - // This class auto-wraps the BlackBox with IO(...), allowing legacy code (where IO(...) wasn't - // required) to build. - override def _compatAutoWrapPorts(): Unit = { - if (!_compatIoPortBound()) { - _bindIoInPlace(io) - } - } - } + type BlackBox = chisel3.internal.LegacyBlackBox type MemBase[T <: Data] = chisel3.MemBase[T] @@ -321,12 +312,6 @@ package object Chisel { this(None, Option(_reset))(moduleCompileOptions) def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions) - - override def _compatAutoWrapPorts(): Unit = { - if (!_compatIoPortBound() && io != null) { - _bindIoInPlace(io) - } - } } val Module = chisel3.Module -- cgit v1.2.3 From 6c6ec7161e8f046fff1cfc68a468ce2f053fdb7f Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Thu, 21 Jan 2021 11:41:20 -0800 Subject: Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModule --- src/main/scala/chisel3/compatibility.scala | 24 +++--------------------- 1 file changed, 3 insertions(+), 21 deletions(-) (limited to 'src/main') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 7066384b..e62cba7d 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -293,29 +293,11 @@ package object Chisel { } import chisel3.CompileOptions - abstract class CompatibilityModule(implicit moduleCompileOptions: CompileOptions) - extends chisel3.internal.LegacyModule()(moduleCompileOptions) { - // This class auto-wraps the Module IO with IO(...), allowing legacy code (where IO(...) wasn't - // required) to build. - // Also provides the clock / reset constructors, which were used before withClock happened. - - // Provide a non-deprecated constructor - def this(override_clock: Option[Clock]=None, override_reset: Option[Bool]=None) - (implicit moduleCompileOptions: CompileOptions) = { - this() - this.override_clock = override_clock - this.override_reset = override_reset - } - def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = - this(Option(_clock), None)(moduleCompileOptions) - def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions) = - this(None, Option(_reset))(moduleCompileOptions) - def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = - this(Option(_clock), Option(_reset))(moduleCompileOptions) - } + @deprecated("Use Chisel.Module", "Chisel 3.5") + type CompatibilityModule = chisel3.internal.LegacyModule val Module = chisel3.Module - type Module = CompatibilityModule + type Module = chisel3.internal.LegacyModule val printf = chisel3.printf -- cgit v1.2.3