From 29f84617ea30c7dd30c9616bcdb9a1894b8a0762 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 15:23:25 -0800
Subject: Eliminate some doc warnings

---
 src/main/scala/chisel3/Driver.scala         | 2 +-
 src/main/scala/chisel3/util/Decoupled.scala | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index a0713379..11a447d1 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -95,7 +95,7 @@ trait BackendCompilationUtilities {
   /** Generates a Verilator invocation to convert Verilog sources to C++
     * simulation sources.
     *
-    * The Verilator prefix will be V$dutFile, and running this will generate
+    * The Verilator prefix will be V\$dutFile, and running this will generate
     * C++ sources and headers as well as a makefile to compile them.
     *
     * @param dutFile name of the DUT .v without the .v extension
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index c9d57759..2f6effbd 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -230,7 +230,7 @@ extends Module(override_reset=override_reset) {
   * @param enq input (enqueue) interface to the queue, also determines width of queue elements
   * @param entries depth (number of elements) of the queue
   *
-  * @returns output (dequeue) interface from the queue
+  * @return output (dequeue) interface from the queue
   *
   * @example {{{
   * consumer.io.in <> Queue(producer.io.out, 16)
-- 
cgit v1.2.3


From b2afa964431c9f109cf10c83d5db49a8d5799b58 Mon Sep 17 00:00:00 2001
From: Stevo
Date: Fri, 18 Nov 2016 10:54:43 -0800
Subject: Shift register enable gates all stages, not just first

Also, remove no-longer-special case for n=1.---
 src/main/scala/chisel3/util/Reg.scala | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 713a3b2e..f41d789c 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -55,10 +55,8 @@ object ShiftRegister
     */
   def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = {
     // The order of tests reflects the expected use cases.
-    if (n == 1) {
-      RegEnable(in, en)
-    } else if (n != 0) {
-      RegNext(apply(in, n-1, en))
+    if (n != 0) {
+      RegEnable(apply(in, n-1, en), en)
     } else {
       in
     }
-- 
cgit v1.2.3


From 6929ca0fc64b562f4852a49df617a1836e083563 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Thu, 27 Oct 2016 14:01:33 -0700
Subject: Change Verilator invocation to use O1

Workaround for:
http://www.veripool.org/issues/1101-Verilator-Fix-SmallName-for-ParamTypeDType
---
 src/main/scala/chisel3/Driver.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 11a447d1..ab51ad25 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -119,13 +119,13 @@ trait BackendCompilationUtilities {
         "-Wno-WIDTH",
         "-Wno-STMTDLY",
         "--trace",
-        "-O0",
+        "-O1",
         "--top-module", topModule,
         "+define+TOP_TYPE=V" + dutFile,
         s"+define+PRINTF_COND=!$topModule.reset",
         s"+define+STOP_COND=!$topModule.reset",
         "-CFLAGS",
-        s"""-Wno-undefined-bool-conversion -O0 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
+        s"""-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
         "-Mdir", dir.toString,
         "--exe", cppHarness.toString)
     System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex
-- 
cgit v1.2.3


From 822160cc8e76e70643fb56707bb39f6f7526b6fd Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Thu, 22 Sep 2016 22:38:33 -0700
Subject: Add support for parameterized BlackBoxes

Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.

Resolves #289
---
 .../scala/chisel3/internal/firrtl/Emitter.scala    | 24 ++++++++++++++++------
 src/main/scala/chisel3/package.scala               | 24 ++++++++++++++++++++++
 2 files changed, 42 insertions(+), 6 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 3fb18893..b8651828 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -2,6 +2,7 @@
 
 package chisel3.internal.firrtl
 import chisel3._
+import chisel3.experimental._
 import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine}
 
 private[chisel3] object Emitter {
@@ -42,6 +43,16 @@ private class Emitter(circuit: Circuit) {
     firrtlLine + e.sourceInfo.makeMessage(" " + _)
   }
 
+  private def emitParam(name: String, p: Param): String = {
+    val str = p match {
+      case IntParam(value) => value.toString
+      case DoubleParam(value) => value.toString
+      case StringParam(str) => "\"" + str + "\""
+      case RawParam(str) => "'" + str + "'"
+    }
+    s"parameter $name = $str"
+  }
+
   // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already.
   private val defnMap = collection.mutable.HashMap[(String, String), Component]()
 
@@ -61,12 +72,13 @@ private class Emitter(circuit: Circuit) {
         body ++= newline + emitPort(p)
       body ++= newline
 
-      m.id match {
-        case _: BlackBox =>
-          // TODO: BlackBoxes should be empty, but funkiness in Module() means
-          // it's not for now. Eventually, this should assert out.
-        case _: Module => for (cmd <- m.commands) {
-          body ++= newline + emit(cmd, m)
+      m match {
+        case bb: DefBlackBox =>
+          // Firrtl extmodule can overrule name
+          body ++= newline + s"defname = ${bb.id.desiredName}"
+          body ++= newline + (bb.params map { case (n, p) => emitParam(n, p) } mkString newline)
+        case mod: DefModule => for (cmd <- mod.commands) {
+          body ++= newline + emit(cmd, mod)
         }
       }
       body ++= newline
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index e0364868..3cdda971 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -179,4 +179,28 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   }
   def getModulePorts(m: Module): Seq[Port] = m.getPorts
   def getFirrtlDirection(d: Data): Direction = chisel3.core.Data.getFirrtlDirection(d)
+
+  /** Package for experimental features, which may have their API changed, be removed, etc.
+    *
+    * Because its contents won't necessarily have the same level of stability and support as
+    * non-experimental, you must explicitly import this package to use its contents.
+    */
+  object experimental {
+    type Param = chisel3.core.Param
+    type IntParam = chisel3.core.IntParam
+    val IntParam = chisel3.core.IntParam
+    type DoubleParam = chisel3.core.DoubleParam
+    val DoubleParam = chisel3.core.DoubleParam
+    type StringParam = chisel3.core.StringParam
+    val StringParam = chisel3.core.StringParam
+    type RawParam = chisel3.core.RawParam
+    val RawParam = chisel3.core.RawParam
+
+    // Implicit conversions for BlackBox Parameters
+    implicit def fromIntToIntParam(x: Int): IntParam = IntParam(BigInt(x))
+    implicit def fromLongToIntParam(x: Long): IntParam = IntParam(BigInt(x))
+    implicit def fromBigIntToIntParam(x: BigInt): IntParam = IntParam(x)
+    implicit def fromDoubleToDoubleParam(x: Double): DoubleParam = DoubleParam(x)
+    implicit def fromStringToStringParam(x: String): StringParam = StringParam(x)
+  }
 }
-- 
cgit v1.2.3


From 22406a589c4a3f8de42a9f5c988201f474c11282 Mon Sep 17 00:00:00 2001
From: chick
Date: Wed, 9 Nov 2016 16:23:52 -0800
Subject: simple test that range interpolator works with UInt factory method

---
 src/main/scala/chisel3/package.scala | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 3cdda971..436534e1 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,3 +1,4 @@
+
 // See LICENSE for license details.
 
 package object chisel3 {    // scalastyle:ignore package.object.name
@@ -11,6 +12,8 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   import chisel3.util._
   import chisel3.internal.firrtl.Port
 
+  import chisel3.internal.firrtl.NumericBound
+
   type Direction = chisel3.core.Direction
   val Input   = chisel3.core.Input
   val Output  = chisel3.core.Output
@@ -156,6 +159,10 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
   }
 
+  implicit class ChiselRange(val sc: StringContext) extends AnyVal {
+    def range(args: Any*): (NumericBound[Int], NumericBound[Int]) = macro chisel3.internal.RangeTransform.apply
+  }
+
   implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3")
-- 
cgit v1.2.3


From 876bc32feca6bd0a2aaec7019fd3d29675ce0255 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 15:23:36 -0800
Subject: Fix open-open range specifier, remove dead code, restyle tests

---
 src/main/scala/chisel3/package.scala | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 436534e1..b49f6dec 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,10 +1,9 @@
-
 // See LICENSE for license details.
 
 package object chisel3 {    // scalastyle:ignore package.object.name
   import scala.language.experimental.macros
 
-  import internal.firrtl.Width
+  import internal.firrtl.{Width, NumericBound}
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
   import util.BitPat
 
@@ -12,8 +11,6 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   import chisel3.util._
   import chisel3.internal.firrtl.Port
 
-  import chisel3.internal.firrtl.NumericBound
-
   type Direction = chisel3.core.Direction
   val Input   = chisel3.core.Input
   val Output  = chisel3.core.Output
-- 
cgit v1.2.3


From e8aea3f4153b58321784ac33734305207570ef75 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 17:51:56 -0800
Subject: Move ChiselRange to experimental

---
 src/main/scala/chisel3/package.scala | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index b49f6dec..29aa6528 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -156,10 +156,6 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
   }
 
-  implicit class ChiselRange(val sc: StringContext) extends AnyVal {
-    def range(args: Any*): (NumericBound[Int], NumericBound[Int]) = macro chisel3.internal.RangeTransform.apply
-  }
-
   implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3")
@@ -206,5 +202,17 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     implicit def fromBigIntToIntParam(x: BigInt): IntParam = IntParam(x)
     implicit def fromDoubleToDoubleParam(x: Double): DoubleParam = DoubleParam(x)
     implicit def fromStringToStringParam(x: String): StringParam = StringParam(x)
+
+    implicit class ChiselRange(val sc: StringContext) extends AnyVal {
+      /** Specifies a range using mathematical range notation. Variables can be interpolated using
+       *  standard string interpolation syntax.
+        * @example {{{
+        * UInt(range"[0, 2)")
+        * UInt(range"[0, $myInt)")
+        * UInt(range"[0, ${myInt + 2})")
+        * }}}
+        */
+      def range(args: Any*): (NumericBound[Int], NumericBound[Int]) = macro chisel3.internal.RangeTransform.apply
+    }
   }
 }
-- 
cgit v1.2.3


From 15a8d3818a1b185051b260ffc82da1fb4a60a45e Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 18:31:24 -0800
Subject: Break out deprecated literal constructors, refactor all the things!

---
 src/main/scala/chisel3/compatibility.scala | 88 ++++++++++++++++--------------
 src/main/scala/chisel3/package.scala       | 88 +++++++++++++++---------------
 2 files changed, 91 insertions(+), 85 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index d0d2ddb4..7157b4d4 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -6,6 +6,7 @@
 package object Chisel {     // scalastyle:ignore package.object.name
   implicit val defaultCompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict
   type Direction = chisel3.core.Direction
+
   val INPUT = chisel3.core.Direction.Input
   val OUTPUT = chisel3.core.Direction.Output
   val NODIR = chisel3.core.Direction.Unspecified
@@ -38,12 +39,51 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val assert = chisel3.core.assert
   val stop = chisel3.core.stop
 
+  trait UIntFactory extends chisel3.core.UIntFactory {
+    import chisel3.internal.firrtl.Width
+
+    /** Create a UInt with a specified width */
+    def width(width: Int): UInt = apply(Width(width))
+
+    /** Create a UInt literal with inferred width. */
+    def apply(n: String): UInt = Lit(n)
+    /** Create a UInt literal with fixed width. */
+    def apply(n: String, width: Int): UInt = Lit(parse(n), width)
+
+    /** Create a UInt literal with specified width. */
+    def apply(value: BigInt, width: Width): UInt = Lit(value, width)
+
+    /** Create a UInt literal with fixed width. */
+    def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+
+    /** Create a UInt with a specified width - compatibility with Chisel2. */
+    // NOTE: This resolves UInt(width = 32)
+    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+    /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
+    def apply(value: BigInt): UInt = apply(value, Width())
+    /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+    def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
+    /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
+    def apply(dir: Direction): UInt = apply(dir, Width())
+    def apply(dir: Direction, wWidth: Width): UInt = {
+      val result = apply(wWidth)
+      dir match {
+        case chisel3.core.Direction.Input => chisel3.core.Input(result)
+        case chisel3.core.Direction.Output => chisel3.core.Output(result)
+        case chisel3.core.Direction.Unspecified => result
+      }
+    }
+
+    /** Create a UInt port with specified width. */
+    def width(width: Width): UInt = apply(width)
+  }
+
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
-  val Bits = chisel3.core.Bits
+  object Bits extends UIntFactory
   type Num[T <: Data] = chisel3.core.Num[T]
   type UInt = chisel3.core.UInt
-  val UInt = chisel3.core.UInt
+  object UInt extends UIntFactory
   type SInt = chisel3.core.SInt
   val SInt = chisel3.core.SInt
   type Bool = chisel3.core.Bool
@@ -68,46 +108,10 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val when = chisel3.core.when
   type WhenContext = chisel3.core.WhenContext
 
-  import chisel3.internal.firrtl.Width
-  /**
-  * These implicit classes allow one to convert scala.Int|scala.BigInt to
-  * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
-  * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
-  * mark a width for the new literal.
-  *
-  * Also provides .asBool to scala.Boolean and .asUInt to String
-  *
-  * Note that, for stylistic reasons, one should avoid extracting immediately
-  * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
-  * confusion (the 1 is a bit length and the 0 is a bit extraction position).
-  * Prefer storing the result and then extracting from it.
-  */
-  implicit class fromIntToLiteral(val x: Int) extends AnyVal {
-    def U: UInt = UInt(BigInt(x), Width())    // scalastyle:ignore method.name
-    def S: SInt = SInt(BigInt(x), Width())    // scalastyle:ignore method.name
-
-    def asUInt(): UInt = UInt(x, Width())
-    def asSInt(): SInt = SInt(x, Width())
-    def asUInt(width: Int): UInt = UInt(x, width)
-    def asSInt(width: Int): SInt = SInt(x, width)
-  }
-
-  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
-    def U: UInt = UInt(x, Width())       // scalastyle:ignore method.name
-    def S: SInt = SInt(x, Width())       // scalastyle:ignore method.name
-
-    def asUInt(): UInt = UInt(x, Width())
-    def asSInt(): SInt = SInt(x, Width())
-    def asUInt(width: Int): UInt = UInt(x, width)
-    def asSInt(width: Int): SInt = SInt(x, width)
-  }
-  implicit class fromStringToLiteral(val x: String) extends AnyVal {
-    def U: UInt = UInt(x)       // scalastyle:ignore method.name
-  }
-  implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
-    def B: Bool = Bool(x)       // scalastyle:ignore method.name
-  }
-
+  implicit class fromtIntToLiteral(override val x: Int) extends chisel3.core.fromIntToLiteral(x)
+  implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
+  implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
+  implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
 
   type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
   val Driver = chisel3.Driver
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 29aa6528..07dcdaca 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -31,10 +31,48 @@ package object chisel3 {    // scalastyle:ignore package.object.name
 
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
-  val Bits = chisel3.core.Bits
+
+  trait UIntFactory extends chisel3.core.UIntFactory {
+    /** Create a UInt with a specified width */
+    def width(width: Int): UInt = apply(Width(width))
+
+    /** Create a UInt literal with inferred width. */
+    def apply(n: String): UInt = Lit(n)
+    /** Create a UInt literal with fixed width. */
+    def apply(n: String, width: Int): UInt = Lit(parse(n), width)
+
+    /** Create a UInt literal with specified width. */
+    def apply(value: BigInt, width: Width): UInt = Lit(value, width)
+
+    /** Create a UInt literal with fixed width. */
+    def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+
+    /** Create a UInt with a specified width - compatibility with Chisel2. */
+    // NOTE: This resolves UInt(width = 32)
+    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+    /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
+    def apply(value: BigInt): UInt = apply(value, Width())
+    /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+    def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
+    /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
+    def apply(dir: Direction): UInt = apply(dir, Width())
+    def apply(dir: Direction, wWidth: Width): UInt = {
+      val result = apply(wWidth)
+      dir match {
+        case chisel3.core.Direction.Input => Input(result)
+        case chisel3.core.Direction.Output => Output(result)
+        case chisel3.core.Direction.Unspecified => result
+      }
+    }
+
+    /** Create a UInt port with specified width. */
+    def width(width: Width): UInt = apply(width)
+  }
+
+  object Bits extends UIntFactory
   type Num[T <: Data] = chisel3.core.Num[T]
   type UInt = chisel3.core.UInt
-  val UInt = chisel3.core.UInt
+  object UInt extends UIntFactory
   type SInt = chisel3.core.SInt
   val SInt = chisel3.core.SInt
   type FixedPoint = chisel3.core.FixedPoint
@@ -113,48 +151,12 @@ package object chisel3 {    // scalastyle:ignore package.object.name
 
   implicit def string2Printable(str: String): Printable = PString(str)
 
-  /**
-  * These implicit classes allow one to convert scala.Int|scala.BigInt to
-  * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
-  * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
-  * mark a width for the new literal.
-  *
-  * Also provides .asBool to scala.Boolean and .asUInt to String
-  *
-  * Note that, for stylistic reasons, one should avoid extracting immediately
-  * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
-  * confusion (the 1 is a bit length and the 0 is a bit extraction position).
-  * Prefer storing the result and then extracting from it.
-  */
-  implicit class fromIntToLiteral(val x: Int) extends AnyVal {
-    def U: UInt = UInt(BigInt(x), Width())    // scalastyle:ignore method.name
-    def S: SInt = SInt(BigInt(x), Width())    // scalastyle:ignore method.name
-
-    def asUInt(): UInt = UInt(x, Width())
-    def asSInt(): SInt = SInt(x, Width())
-    def asUInt(width: Int): UInt = UInt(x, width)
-    def asSInt(width: Int): SInt = SInt(x, width)
-  }
+  implicit class fromtIntToLiteral(override val x: Int) extends chisel3.core.fromIntToLiteral(x)
+  implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
+  implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
+  implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
+  implicit class fromDoubleToLiteral(override val x: Double) extends chisel3.core.fromDoubleToLiteral(x)
 
-  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
-    def U: UInt = UInt(x, Width())    // scalastyle:ignore method.name
-    def S: SInt = SInt(x, Width())    // scalastyle:ignore method.name
-
-    def asUInt(): UInt = UInt(x, Width())
-    def asSInt(): SInt = SInt(x, Width())
-    def asUInt(width: Int): UInt = UInt(x, width)
-    def asSInt(width: Int): SInt = SInt(x, width)
-  }
-  implicit class fromStringToLiteral(val x: String) extends AnyVal {
-    def U: UInt = UInt(x)    // scalastyle:ignore method.name
-  }
-  implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
-    def B: Bool = Bool(x)    // scalastyle:ignore method.name
-  }
-
-  implicit class fromDoubleToLiteral(val x: Double) extends AnyVal {
-    def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
-  }
 
   implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-- 
cgit v1.2.3


From e0b277a40693476247a68e7c52672b547d7ceb17 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 18:47:36 -0800
Subject: Deprecate things, split more things

---
 src/main/scala/chisel3/compatibility.scala | 12 ++++++-----
 src/main/scala/chisel3/package.scala       | 34 ++++++++++++++----------------
 2 files changed, 23 insertions(+), 23 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 7157b4d4..ac0caa45 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -42,13 +42,12 @@ package object Chisel {     // scalastyle:ignore package.object.name
   trait UIntFactory extends chisel3.core.UIntFactory {
     import chisel3.internal.firrtl.Width
 
-    /** Create a UInt with a specified width */
-    def width(width: Int): UInt = apply(Width(width))
-
     /** Create a UInt literal with inferred width. */
-    def apply(n: String): UInt = Lit(n)
+    def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
+        chisel3.core.fromStringToLiteral.parsedWidth(n))
     /** Create a UInt literal with fixed width. */
-    def apply(n: String, width: Int): UInt = Lit(parse(n), width)
+    def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
+        Width(width))
 
     /** Create a UInt literal with specified width. */
     def apply(value: BigInt, width: Width): UInt = Lit(value, width)
@@ -74,6 +73,9 @@ package object Chisel {     // scalastyle:ignore package.object.name
       }
     }
 
+    /** Create a UInt with a specified width */
+    def width(width: Int): UInt = apply(Width(width))
+
     /** Create a UInt port with specified width. */
     def width(width: Width): UInt = apply(width)
   }
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 07dcdaca..84a4779e 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -33,39 +33,37 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type Bits = chisel3.core.Bits
 
   trait UIntFactory extends chisel3.core.UIntFactory {
-    /** Create a UInt with a specified width */
-    def width(width: Int): UInt = apply(Width(width))
-
     /** Create a UInt literal with inferred width. */
-    def apply(n: String): UInt = Lit(n)
+    @deprecated("chisel3, will be removed by end of 2016, use n.U")
+    def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
+        chisel3.core.fromStringToLiteral.parsedWidth(n))
     /** Create a UInt literal with fixed width. */
-    def apply(n: String, width: Int): UInt = Lit(parse(n), width)
+    @deprecated("chisel3, will be removed by end of 2016, use n.U(width: Width)")
+    def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
+        Width(width))
 
     /** Create a UInt literal with specified width. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.U(width: Width)")
     def apply(value: BigInt, width: Width): UInt = Lit(value, width)
 
     /** Create a UInt literal with fixed width. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.U(width: Width)")
     def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
 
     /** Create a UInt with a specified width - compatibility with Chisel2. */
-    // NOTE: This resolves UInt(width = 32)
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
     def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.U")
     def apply(value: BigInt): UInt = apply(value, Width())
-    /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
-    def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
-    /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
-    def apply(dir: Direction): UInt = apply(dir, Width())
-    def apply(dir: Direction, wWidth: Width): UInt = {
-      val result = apply(wWidth)
-      dir match {
-        case chisel3.core.Direction.Input => Input(result)
-        case chisel3.core.Direction.Output => Output(result)
-        case chisel3.core.Direction.Unspecified => result
-      }
-    }
+
+    /** Create a UInt with a specified width */
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
+    def width(width: Int): UInt = apply(Width(width))
 
     /** Create a UInt port with specified width. */
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
     def width(width: Width): UInt = apply(width)
   }
 
-- 
cgit v1.2.3


From 9e32a39bda3fba11e6b0990e6ad5e7e17b5d8364 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 18:54:44 -0800
Subject: Refactor SInt WIP

---
 src/main/scala/chisel3/compatibility.scala | 39 ++++++++++++++++++++++++++---
 src/main/scala/chisel3/package.scala       | 40 ++++++++++++++++++++++++------
 2 files changed, 69 insertions(+), 10 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index ac0caa45..69d02f9c 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -4,6 +4,8 @@
 // moving to the more standard package naming convention chisel3 (lowercase c).
 
 package object Chisel {     // scalastyle:ignore package.object.name
+  import chisel3.internal.firrtl.Width
+
   implicit val defaultCompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict
   type Direction = chisel3.core.Direction
 
@@ -40,8 +42,6 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val stop = chisel3.core.stop
 
   trait UIntFactory extends chisel3.core.UIntFactory {
-    import chisel3.internal.firrtl.Width
-
     /** Create a UInt literal with inferred width. */
     def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         chisel3.core.fromStringToLiteral.parsedWidth(n))
@@ -80,6 +80,39 @@ package object Chisel {     // scalastyle:ignore package.object.name
     def width(width: Width): UInt = apply(width)
   }
 
+  trait SIntFactory extends chisel3.core.SIntFactory {
+    /** Create a SInt type or port with fixed width. */
+    def width(width: Int): SInt = apply(Width(width))
+    /** Create an SInt type with specified width. */
+    def width(width: Width): SInt = apply(width)
+
+    /** Create an SInt literal with inferred width. */
+    def apply(value: BigInt): SInt = Lit(value)
+    /** Create an SInt literal with fixed width. */
+    def apply(value: BigInt, width: Int): SInt = Lit(value, width)
+
+    /** Create an SInt literal with specified width. */
+    def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+
+    def Lit(value: BigInt): SInt = Lit(value, Width())
+    def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
+
+    /** Create a SInt with a specified width - compatibility with Chisel2. */
+    def apply(dir: Option[Direction] = None, width: Int): SInt = apply(Width(width))
+    /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
+    def apply(dir: Direction, width: Int): SInt = apply(dir, Width(width))
+    /** Create a SInt with a specified direction, but unspecified width - compatibility with Chisel2. */
+    def apply(dir: Direction): SInt = apply(dir, Width())
+    def apply(dir: Direction, wWidth: Width): SInt = {
+      val result = apply(wWidth)
+      dir match {
+        case chisel3.core.Direction.Input => chisel3.core.Input(result)
+        case chisel3.core.Direction.Output => chisel3.core.Output(result)
+        case chisel3.core.Direction.Unspecified => result
+      }
+    }
+  }
+
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
   object Bits extends UIntFactory
@@ -87,7 +120,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   type UInt = chisel3.core.UInt
   object UInt extends UIntFactory
   type SInt = chisel3.core.SInt
-  val SInt = chisel3.core.SInt
+  object SInt extends SIntFactory
   type Bool = chisel3.core.Bool
   val Bool = chisel3.core.Bool
   val Mux = chisel3.core.Mux
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 84a4779e..1161a1ca 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -38,20 +38,20 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         chisel3.core.fromStringToLiteral.parsedWidth(n))
     /** Create a UInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use n.U(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use n.U(width.W)")
     def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         Width(width))
 
     /** Create a UInt literal with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use value.U(width)")
     def apply(value: BigInt, width: Width): UInt = Lit(value, width)
 
     /** Create a UInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use value.U(width.W)")
     def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
 
     /** Create a UInt with a specified width - compatibility with Chisel2. */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width.W)")
     def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
 
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
@@ -59,20 +59,46 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     def apply(value: BigInt): UInt = apply(value, Width())
 
     /** Create a UInt with a specified width */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width.W)")
     def width(width: Int): UInt = apply(Width(width))
 
     /** Create a UInt port with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width)")
     def width(width: Width): UInt = apply(width)
   }
 
+  trait SIntFactory extends chisel3.core.SIntFactory {
+    /** Create a SInt type or port with fixed width. */
+    @deprecated("chisel3, will be removed by end of 2016, use SInt(width.W)")
+    def width(width: Int): SInt = apply(Width(width))
+    /** Create an SInt type with specified width. */
+    @deprecated("chisel3, will be removed by end of 2016, use SInt(width)")
+    def width(width: Width): SInt = apply(width)
+
+    /** Create an SInt literal with inferred width. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.S")
+    def apply(value: BigInt): SInt = Lit(value)
+    /** Create an SInt literal with fixed width. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.S(width.W)")
+    def apply(value: BigInt, width: Int): SInt = Lit(value, width)
+
+    /** Create an SInt literal with specified width. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.S(width)")
+    def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+
+    @deprecated("chisel3, will be removed by end of 2016, use value.S")
+    def Lit(value: BigInt): SInt = Lit(value, Width())
+
+    @deprecated("chisel3, will be removed by end of 2016, use value.S(width)")
+    def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
+  }
+
   object Bits extends UIntFactory
   type Num[T <: Data] = chisel3.core.Num[T]
   type UInt = chisel3.core.UInt
   object UInt extends UIntFactory
   type SInt = chisel3.core.SInt
-  val SInt = chisel3.core.SInt
+  object SInt extends SIntFactory
   type FixedPoint = chisel3.core.FixedPoint
   val FixedPoint = chisel3.core.FixedPoint
   type Bool = chisel3.core.Bool
-- 
cgit v1.2.3


From b0cc0c93a80aec5bed54cfb11923636c09b7e180 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 11:21:59 -0800
Subject: SInt conversion finished, everything builds again

---
 src/main/scala/chisel3/compatibility.scala | 1 +
 src/main/scala/chisel3/package.scala       | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 69d02f9c..a9365ac3 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -147,6 +147,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
   implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
   implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
+  implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
 
   type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
   val Driver = chisel3.Driver
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 1161a1ca..1a100480 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -180,7 +180,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
   implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
   implicit class fromDoubleToLiteral(override val x: Double) extends chisel3.core.fromDoubleToLiteral(x)
-
+  implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
 
   implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-- 
cgit v1.2.3


From cd904da0aa0e96ba679906a3ee5dbdc068eace48 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 11:33:20 -0800
Subject: Restyle Bool constructors, move compatibility deprecations into
 compatibility package object

---
 src/main/scala/chisel3/compatibility.scala         | 48 ++++++++++++++++++++--
 src/main/scala/chisel3/compatibility/Main.scala    | 19 ---------
 src/main/scala/chisel3/compatibility/debug.scala   | 10 -----
 .../chisel3/compatibility/throwException.scala     | 14 -------
 src/main/scala/chisel3/package.scala               |  9 +++-
 5 files changed, 52 insertions(+), 48 deletions(-)
 delete mode 100644 src/main/scala/chisel3/compatibility/Main.scala
 delete mode 100644 src/main/scala/chisel3/compatibility/debug.scala
 delete mode 100644 src/main/scala/chisel3/compatibility/throwException.scala

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index a9365ac3..9d0e266b 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -113,6 +113,22 @@ package object Chisel {     // scalastyle:ignore package.object.name
     }
   }
 
+  trait BoolFactory extends chisel3.core.BoolFactory {
+    /** Creates Bool literal.
+     */
+    def apply(x: Boolean): Bool = Lit(x)
+
+    /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+    def apply(dir: Direction): Bool = {
+      val result = apply()
+      dir match {
+        case chisel3.core.Direction.Input => chisel3.core.Input(result)
+        case chisel3.core.Direction.Output => chisel3.core.Output(result)
+        case chisel3.core.Direction.Unspecified => result
+      }
+    }
+  }
+
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
   object Bits extends UIntFactory
@@ -122,7 +138,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   type SInt = chisel3.core.SInt
   object SInt extends SIntFactory
   type Bool = chisel3.core.Bool
-  val Bool = chisel3.core.Bool
+  object Bool extends BoolFactory
   val Mux = chisel3.core.Mux
 
   type BlackBox = chisel3.core.BlackBox
@@ -152,9 +168,33 @@ package object Chisel {     // scalastyle:ignore package.object.name
   type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
   val Driver = chisel3.Driver
   val ImplicitConversions = chisel3.util.ImplicitConversions
-  val chiselMain = chisel3.compatibility.chiselMain
-  val throwException = chisel3.compatibility.throwException
-  val debug = chisel3.compatibility.debug
+
+  object chiselMain {
+    import java.io.File
+
+    def apply[T <: Module](args: Array[String], gen: () => T): Unit =
+      Predef.assert(false, "No more chiselMain in Chisel3")
+
+    def run[T <: Module] (args: Array[String], gen: () => T): Unit = {
+      val circuit = Driver.elaborate(gen)
+      Driver.parseArgs(args)
+      val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
+      Driver.dumpFirrtl(circuit, Option(output_file))
+    }
+  }
+
+  @deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
+  object debug {  // scalastyle:ignore object.name
+    def apply (arg: Data): Data = arg
+  }
+
+  @throws(classOf[Exception])
+  object throwException {
+    def apply(s: String, t: Throwable = null) = {
+      val xcpt = new Exception(s, t)
+      throw xcpt
+    }
+  }
 
   object testers {    // scalastyle:ignore object.name
     type BasicTester = chisel3.testers.BasicTester
diff --git a/src/main/scala/chisel3/compatibility/Main.scala b/src/main/scala/chisel3/compatibility/Main.scala
deleted file mode 100644
index a41599a3..00000000
--- a/src/main/scala/chisel3/compatibility/Main.scala
+++ /dev/null
@@ -1,19 +0,0 @@
-// See LICENSE for license details.
-
-package chisel3.compatibility
-
-import java.io.File
-
-import chisel3._
-
-@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain {
-  def apply[T <: Module](args: Array[String], gen: () => T): Unit =
-    Predef.assert(false, "No more chiselMain in Chisel3")
-
-  def run[T <: Module] (args: Array[String], gen: () => T): Unit = {
-    val circuit = Driver.elaborate(gen)
-    Driver.parseArgs(args)
-    val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
-    Driver.dumpFirrtl(circuit, Option(output_file))
-  }
-}
diff --git a/src/main/scala/chisel3/compatibility/debug.scala b/src/main/scala/chisel3/compatibility/debug.scala
deleted file mode 100644
index d9f6e4b0..00000000
--- a/src/main/scala/chisel3/compatibility/debug.scala
+++ /dev/null
@@ -1,10 +0,0 @@
-// See LICENSE for license details.
-
-package chisel3.compatibility
-
-import chisel3.core._
-
-@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
-object debug {  // scalastyle:ignore object.name
-  def apply (arg: Data): Data = arg
-}
diff --git a/src/main/scala/chisel3/compatibility/throwException.scala b/src/main/scala/chisel3/compatibility/throwException.scala
deleted file mode 100644
index 3e8b33e6..00000000
--- a/src/main/scala/chisel3/compatibility/throwException.scala
+++ /dev/null
@@ -1,14 +0,0 @@
-// See LICENSE for license details.
-
-package chisel3.compatibility
-
-import chisel3._
-
-@deprecated("throwException doesn't exist in Chisel3", "3.0.0")
-@throws(classOf[Exception])
-object throwException {
-  def apply(s: String, t: Throwable = null) = {
-    val xcpt = new Exception(s, t)
-    throw xcpt
-  }
-}
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 1a100480..8ac76867 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -93,6 +93,13 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
   }
 
+  trait BoolFactory extends chisel3.core.BoolFactory {
+    /** Creates Bool literal.
+     */
+    @deprecated("chisel3, will be removed by end of 2016, use x.B")
+    def apply(x: Boolean): Bool = Lit(x)
+  }
+
   object Bits extends UIntFactory
   type Num[T <: Data] = chisel3.core.Num[T]
   type UInt = chisel3.core.UInt
@@ -102,7 +109,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type FixedPoint = chisel3.core.FixedPoint
   val FixedPoint = chisel3.core.FixedPoint
   type Bool = chisel3.core.Bool
-  val Bool = chisel3.core.Bool
+  object Bool extends BoolFactory
   val Mux = chisel3.core.Mux
 
   type BlackBox = chisel3.core.BlackBox
-- 
cgit v1.2.3


From 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:01:03 -0800
Subject: Restyle a lot of test code, mainly with regex

---
 src/main/scala/chisel3/compatibility.scala         |  6 +++
 src/main/scala/chisel3/package.scala               | 50 +++++++++++++++-------
 src/main/scala/chisel3/util/Arbiter.scala          | 28 ++++++------
 src/main/scala/chisel3/util/BitPat.scala           |  2 +-
 src/main/scala/chisel3/util/Bitwise.scala          |  6 +--
 src/main/scala/chisel3/util/CircuitMath.scala      |  8 ++--
 src/main/scala/chisel3/util/Counter.scala          | 14 +++---
 src/main/scala/chisel3/util/Decoupled.scala        | 24 +++++------
 .../scala/chisel3/util/ImplicitConversions.scala   |  4 +-
 src/main/scala/chisel3/util/LFSR.scala             |  4 +-
 src/main/scala/chisel3/util/OneHot.scala           | 10 ++---
 src/main/scala/chisel3/util/Reg.scala              |  2 +-
 src/main/scala/chisel3/util/Valid.scala            |  2 +-
 13 files changed, 92 insertions(+), 68 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 9d0e266b..625628dd 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -41,6 +41,8 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val assert = chisel3.core.assert
   val stop = chisel3.core.stop
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
     def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
@@ -80,6 +82,8 @@ package object Chisel {     // scalastyle:ignore package.object.name
     def width(width: Width): UInt = apply(width)
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    */
   trait SIntFactory extends chisel3.core.SIntFactory {
     /** Create a SInt type or port with fixed width. */
     def width(width: Int): SInt = apply(Width(width))
@@ -113,6 +117,8 @@ package object Chisel {     // scalastyle:ignore package.object.name
     }
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    */
   trait BoolFactory extends chisel3.core.BoolFactory {
     /** Creates Bool literal.
      */
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 8ac76867..8b5b8a46 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -32,71 +32,89 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    * These will be removed very soon. It's recommended you move your code soon.
+    *
+    * Some recommended regex replacements:
+    * (note: these are not guaranteed to handle all edge cases! check all replacements!)
+    * Bool((true|false)) => $1.B
+    * UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => UInt($1.W)
+    * (UInt|SInt|Bits).width\((\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $1($2.W)
+    * (U|S)Int\((-?\d+|0[xX][0-9a-fA-F]+)\) => $2.$1
+    * UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width)?\s*=\s*(\d+)\) => $1.U($2.W)
+    * (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1
+    */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
-    @deprecated("chisel3, will be removed by end of 2016, use n.U")
+    @deprecated("use n.U", "chisel3, will be removed by end of 2016")
     def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         chisel3.core.fromStringToLiteral.parsedWidth(n))
     /** Create a UInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use n.U(width.W)")
+    @deprecated("use n.U(width.W)", "chisel3, will be removed by end of 2016")
     def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         Width(width))
 
     /** Create a UInt literal with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U(width)")
+    @deprecated("use value.U(width)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Width): UInt = Lit(value, width)
 
     /** Create a UInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U(width.W)")
+    @deprecated("use value.U(width.W)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
 
     /** Create a UInt with a specified width - compatibility with Chisel2. */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width.W)")
+    @deprecated("use UInt(width.W)", "chisel3, will be removed by end of 2016")
     def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
 
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U")
+    @deprecated("use value.U", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt): UInt = apply(value, Width())
 
     /** Create a UInt with a specified width */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width.W)")
+    @deprecated("use UInt(width.W)", "chisel3, will be removed by end of 2016")
     def width(width: Int): UInt = apply(Width(width))
 
     /** Create a UInt port with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width)")
+    @deprecated("use UInt(width)", "chisel3, will be removed by end of 2016")
     def width(width: Width): UInt = apply(width)
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    * These will be removed very soon. It's recommended you move your code soon.
+    */
   trait SIntFactory extends chisel3.core.SIntFactory {
     /** Create a SInt type or port with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use SInt(width.W)")
+    @deprecated("use SInt(width.W)", "chisel3, will be removed by end of 2016")
     def width(width: Int): SInt = apply(Width(width))
     /** Create an SInt type with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use SInt(width)")
+    @deprecated("use SInt(width)", "chisel3, will be removed by end of 2016")
     def width(width: Width): SInt = apply(width)
 
     /** Create an SInt literal with inferred width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.S")
+    @deprecated("use value.S", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt): SInt = Lit(value)
     /** Create an SInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.S(width.W)")
+    @deprecated("use value.S(width.W)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Int): SInt = Lit(value, width)
 
     /** Create an SInt literal with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.S(width)")
+    @deprecated("use value.S(width)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Width): SInt = Lit(value, width)
 
-    @deprecated("chisel3, will be removed by end of 2016, use value.S")
+    @deprecated("use value.S", "chisel3, will be removed by end of 2016")
     def Lit(value: BigInt): SInt = Lit(value, Width())
 
-    @deprecated("chisel3, will be removed by end of 2016, use value.S(width)")
+    @deprecated("use value.S(width)", "chisel3, will be removed by end of 2016")
     def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    * These will be removed very soon. It's recommended you move your code soon.
+    */
   trait BoolFactory extends chisel3.core.BoolFactory {
     /** Creates Bool literal.
      */
-    @deprecated("chisel3, will be removed by end of 2016, use x.B")
+    @deprecated("use x.B", "chisel3, will be removed by end of 2016")
     def apply(x: Boolean): Bool = Lit(x)
   }
 
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 89bb644a..d755b620 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -18,7 +18,7 @@ import chisel3.core.ExplicitCompileOptions.NotStrict
 class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
   val in  = Flipped(Vec(n, Decoupled(gen)))
   val out = Decoupled(gen)
-  val chosen = Output(UInt.width(log2Up(n)))
+  val chosen = Output(UInt(log2Up(n).W))
 }
 
 /** Arbiter Control determining which producer has access
@@ -26,8 +26,8 @@ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
 private object ArbiterCtrl {
   def apply(request: Seq[Bool]): Seq[Bool] = request.length match {
     case 0 => Seq()
-    case 1 => Seq(Bool(true))
-    case _ => Bool(true) +: request.tail.init.scanLeft(request.head)(_ || _).map(!_)
+    case 1 => Seq(true.B)
+    case _ => true.B +: request.tail.init.scanLeft(request.head)(_ || _).map(!_)
   }
 }
 
@@ -43,8 +43,8 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
   if (count > 1) {
     val lockCount = Counter(count)
     val lockIdx = Reg(UInt())
-    val locked = lockCount.value =/= UInt(0)
-    val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
+    val locked = lockCount.value =/= 0.U
+    val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(true.B)
 
     when (io.out.fire() && wantsLock) {
       lockIdx := io.chosen
@@ -53,7 +53,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 
     when (locked) { io.chosen := lockIdx }
     for ((in, (g, i)) <- io.in zip grant.zipWithIndex)
-      in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready
+      in.ready := Mux(locked, lockIdx === i.asUInt, g) && io.out.ready
   } else {
     for ((in, g) <- io.in zip grant)
       in.ready := g && io.out.ready
@@ -63,7 +63,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   lazy val lastGrant = RegEnable(io.chosen, io.out.fire())
-  lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
+  lazy val grantMask = (0 until n).map(_.asUInt > lastGrant)
   lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
 
   override def grant: Seq[Bool] = {
@@ -71,20 +71,20 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[
     (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n))
   }
 
-  override lazy val choice = Wire(init=UInt(n-1))
+  override lazy val choice = Wire(init=(n-1).asUInt)
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt(i) }
+    when (io.in(i).valid) { choice := i.asUInt }
   for (i <- n-1 to 1 by -1)
-    when (validMask(i)) { choice := UInt(i) }
+    when (validMask(i)) { choice := i.asUInt }
 }
 
 class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
 
-  override lazy val choice = Wire(init=UInt(n-1))
+  override lazy val choice = Wire(init=(n-1).asUInt)
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt(i) }
+    when (io.in(i).valid) { choice := i.asUInt }
 }
 
 /** Hardware module that is used to sequence n producers into 1 consumer.
@@ -112,11 +112,11 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
 class Arbiter[T <: Data](gen: T, n: Int) extends Module {
   val io = IO(new ArbiterIO(gen, n))
 
-  io.chosen := UInt(n-1)
+  io.chosen := (n-1).asUInt
   io.out.bits := io.in(n-1).bits
   for (i <- n-2 to 0 by -1) {
     when (io.in(i).valid) {
-      io.chosen := UInt(i)
+      io.chosen := i.asUInt
       io.out.bits := io.in(i).bits
     }
   }
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index e58258c7..9c9909cd 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -57,7 +57,7 @@ object BitPat {
     */
   def bitPatToUInt(x: BitPat): UInt = {
     require(x.mask == (BigInt(1) << x.getWidth) - 1)
-    UInt(x.value, x.getWidth)
+    x.value.asUInt(x.getWidth.W)
   }
 
   /** Allows UInts to be used where a BitPat is expected, useful for when an
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 289d27b1..22326972 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -38,10 +38,10 @@ object Fill {
     */
   def apply(n: Int, x: UInt): UInt = {
     n match {
-      case 0 => UInt.width(0)
+      case 0 => UInt(0.W)
       case 1 => x
       case _ if x.isWidthKnown && x.getWidth == 1 =>
-        Mux(x.toBool, UInt((BigInt(1) << n) - 1, n), UInt(0, n))
+        Mux(x.toBool, ((BigInt(1) << n) - 1).asUInt(n.W), 0.U(n.W))
       case _ if n > 1 =>
         val p2 = Array.ofDim[UInt](log2Up(n + 1))
         p2(0) = x
@@ -61,7 +61,7 @@ object Reverse {
       // This esoterica improves simulation performance
       var res = in
       var shift = length >> 1
-      var mask = UInt((BigInt(1) << length) - 1, length)
+      var mask = ((BigInt(1) << length) - 1).asUInt(length.W)
       do {
         mask = mask ^ (mask(length-shift-1,0) << shift)
         res = ((res >> shift) & mask) | ((res(length-shift-1,0) << shift) & ~mask)
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index d478e10e..83e5feb1 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -10,15 +10,15 @@ import chisel3._
 object Log2 {
   /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
     *
-    * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3)
+    * @note The result is truncated, so e.g. Log2(13.U) === 3.U
     */
   def apply(x: Bits, width: Int): UInt = {
     if (width < 2) {
-      UInt(0)
+      0.U
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), UInt(width-1), apply(x, width-1))
+      Mux(x(width-1), UInt((width-1).W), apply(x, width-1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
       val hi = x(width-1, mid)
@@ -30,7 +30,7 @@ object Log2 {
 
   /** Returns the base-2 integer logarithm of an UInt.
     *
-    * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3)
+    * @note The result is truncated, so e.g. Log2(13.U) === 3.U
     */
   def apply(x: Bits): UInt = apply(x, x.getWidth)
 
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index ba66d667..6d59eaaf 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -12,7 +12,7 @@ import chisel3._
   */
 class Counter(val n: Int) {
   require(n >= 0)
-  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0)
+  val value = if (n > 1) Reg(init=0.U(log2Up(n).W)) else 0.U
 
   /** Increment the counter, returning whether the counter currently is at the
     * maximum and will wrap. The incremented value is registered and will be
@@ -20,14 +20,14 @@ class Counter(val n: Int) {
     */
   def inc(): Bool = {
     if (n > 1) {
-      val wrap = value === UInt(n-1)
-      value := value + UInt(1)
+      val wrap = value === (n-1).asUInt
+      value := value + 1.U
       if (!isPow2(n)) {
-        when (wrap) { value := UInt(0) }
+        when (wrap) { value := 0.U }
       }
       wrap
     } else {
-      Bool(true)
+      true.B
     }
   }
 }
@@ -46,9 +46,9 @@ object Counter
     * maximum and the condition is true).
     *
     * @example {{{
-    * val countOn = Bool(true) // increment counter every clock cycle
+    * val countOn = true.B // increment counter every clock cycle
     * val (counterValue, counterWrap) = Counter(countOn, 4)
-    * when (counterValue === UInt(3)) {
+    * when (counterValue === 3.U) {
     *   ...
     * }
     * }}}
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 2f6effbd..fcda6943 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -32,7 +32,7 @@ object ReadyValidIO {
       * @return    dat.
       */
     def enq(dat: T): T = {
-      target.valid := Bool(true)
+      target.valid := true.B
       target.bits := dat
       dat
     }
@@ -40,7 +40,7 @@ object ReadyValidIO {
     /** Indicate no enqueue occurs.  Valid is set to false, and all bits are set to zero.
       */
     def noenq(): Unit = {
-      target.valid := Bool(false)
+      target.valid := false.B
       // We want the type from the following, not any existing binding.
       target.bits := target.bits.cloneType.fromBits(0.asUInt)
     }
@@ -51,14 +51,14 @@ object ReadyValidIO {
       * @return the data for this device,
       */
     def deq(): T = {
-      target.ready := Bool(true)
+      target.ready := true.B
       target.bits
     }
 
     /** Indicate no dequeue occurs. Ready is set to false
       */
     def nodeq(): Unit = {
-      target.ready := Bool(false)
+      target.ready := false.B
     }
   }
 }
@@ -144,7 +144,7 @@ class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
   val deq = EnqIO(gen)
   /** The current amount of data in the queue */
-  val count = Output(UInt.width(log2Up(entries + 1)))
+  val count = Output(UInt(log2Up(entries + 1).W))
 
   override def cloneType = new QueueIO(gen, entries).asInstanceOf[this.type]
 }
@@ -177,7 +177,7 @@ extends Module(override_reset=override_reset) {
   val ram = Mem(entries, gen)
   val enq_ptr = Counter(entries)
   val deq_ptr = Counter(entries)
-  val maybe_full = Reg(init=Bool(false))
+  val maybe_full = Reg(init=false.B)
 
   val ptr_match = enq_ptr.value === deq_ptr.value
   val empty = ptr_match && !maybe_full
@@ -201,16 +201,16 @@ extends Module(override_reset=override_reset) {
   io.deq.bits := ram(deq_ptr.value)
 
   if (flow) {
-    when (io.enq.valid) { io.deq.valid := Bool(true) }
+    when (io.enq.valid) { io.deq.valid := true.B }
     when (empty) {
       io.deq.bits := io.enq.bits
-      do_deq := Bool(false)
-      when (io.deq.ready) { do_enq := Bool(false) }
+      do_deq := false.B
+      when (io.deq.ready) { do_enq := false.B }
     }
   }
 
   if (pipe) {
-    when (io.deq.ready) { io.enq.ready := Bool(true) }
+    when (io.deq.ready) { io.enq.ready := true.B }
   }
 
   val ptr_diff = enq_ptr.value - deq_ptr.value
@@ -219,9 +219,9 @@ extends Module(override_reset=override_reset) {
   } else {
     io.count := Mux(ptr_match,
                     Mux(maybe_full,
-                      UInt(entries), UInt(0)),
+                      entries.asUInt, 0.U),
                     Mux(deq_ptr.value > enq_ptr.value,
-                      UInt(entries) + ptr_diff, ptr_diff))
+                      entries.asUInt + ptr_diff, ptr_diff))
   }
 }
 
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 4d816a19..7f715ad4 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -5,6 +5,6 @@ package chisel3.util
 import chisel3._
 
 object ImplicitConversions {
-  implicit def intToUInt(x: Int): UInt = UInt(x)
-  implicit def booleanToBool(x: Boolean): Bool = Bool(x)
+  implicit def intToUInt(x: Int): UInt = chisel3.core.fromIntToLiteral(x).asUInt
+  implicit def booleanToBool(x: Boolean): Bool = x.asBool
 }
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index fedbf194..83dc907d 100644
--- a/src/main/scala/chisel3/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -15,9 +15,9 @@ object LFSR16 {
     *
     * @param increment optional control to gate when the LFSR updates.
     */
-  def apply(increment: Bool = Bool(true)): UInt = {
+  def apply(increment: Bool = true.B): UInt = {
     val width = 16
-    val lfsr = Reg(init=UInt(1, width))
+    val lfsr = Reg(init=1.U(width.W))
     when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
     lfsr
   }
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 53ba8c3d..7dd0c68b 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -35,7 +35,7 @@ object OHToUInt {
   * Multiple bits may be high in the input.
   */
 object PriorityEncoder {
-  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
+  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(_.asUInt))
   def apply(in: Bits): UInt = apply(in.toBools)
 }
 
@@ -44,9 +44,9 @@ object PriorityEncoder {
 object UIntToOH {
   def apply(in: UInt, width: Int = -1): UInt =
     if (width == -1) {
-      UInt(1) << in
+      1.U << in
     } else {
-      (UInt(1) << in(log2Up(width)-1,0))(width-1,0)
+      (1.U << in(log2Up(width)-1,0))(width-1,0)
     }
 }
 
@@ -55,8 +55,8 @@ object UIntToOH {
   */
 object PriorityEncoderOH {
   private def encode(in: Seq[Bool]): UInt = {
-    val outs = Seq.tabulate(in.size)(i => UInt(BigInt(1) << i, in.size))
-    PriorityMux(in :+ Bool(true), outs :+ UInt(0, in.size))
+    val outs = Seq.tabulate(in.size)(i => (BigInt(1) << i).asUInt(in.size.W))
+    PriorityMux(in :+ true.B, outs :+ 0.U(in.size.W))
   }
   def apply(in: Seq[Bool]): Seq[Bool] = {
     val enc = encode(in)
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index f41d789c..00005e3a 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -53,7 +53,7 @@ object ShiftRegister
     * @param n number of cycles to delay
     * @param en enable the shift
     */
-  def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = {
+  def apply[T <: Data](in: T, n: Int, en: Bool = true.B): T = {
     // The order of tests reflects the expected use cases.
     if (n != 0) {
       RegEnable(apply(in, n-1, en), en)
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 3d153a2a..49a6f515 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -41,7 +41,7 @@ object Pipe
       out.bits <> enqBits
       out
     } else {
-      val v = Reg(Bool(), next=enqValid, init=Bool(false))
+      val v = Reg(Bool(), next=enqValid, init=false.B)
       val b = RegEnable(enqBits, enqValid)
       apply(v, b, latency-1)
     }
-- 
cgit v1.2.3


From 73906fcc796b259c81d5df7733968b77fbb81ba8 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:06:57 -0800
Subject: All remaining automatable regex re-styles

---
 src/main/scala/chisel3/package.scala | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 8b5b8a46..5b02be34 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -41,8 +41,9 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     * UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => UInt($1.W)
     * (UInt|SInt|Bits).width\((\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $1($2.W)
     * (U|S)Int\((-?\d+|0[xX][0-9a-fA-F]+)\) => $2.$1
-    * UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width)?\s*=\s*(\d+)\) => $1.U($2.W)
-    * (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1
+    * UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $1.U($2.W)
+    * (UInt|SInt|Bool)\(([_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1
+    * (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1($3.W)
     */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
-- 
cgit v1.2.3


From d89b54acc5a41dcc7498d97af314e58f6cd891c8 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:31:23 -0800
Subject: Refactor some code

---
 src/main/scala/chisel3/compatibility.scala | 47 +++++++++++++++---------------
 src/main/scala/chisel3/package.scala       | 32 ++++++++++----------
 2 files changed, 39 insertions(+), 40 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 625628dd..fbe37f50 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -45,29 +45,28 @@ package object Chisel {     // scalastyle:ignore package.object.name
     */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
-    def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
-        chisel3.core.fromStringToLiteral.parsedWidth(n))
+    def apply(n: String): UInt = n.asUInt
     /** Create a UInt literal with fixed width. */
-    def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
-        Width(width))
+    def apply(n: String, width: Int): UInt = n.asUInt(width.W)
 
     /** Create a UInt literal with specified width. */
-    def apply(value: BigInt, width: Width): UInt = Lit(value, width)
+    def apply(value: BigInt, width: Width): UInt = value.asUInt(width)
 
     /** Create a UInt literal with fixed width. */
-    def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+    def apply(value: BigInt, width: Int): UInt = value.asUInt(width.W)
 
     /** Create a UInt with a specified width - compatibility with Chisel2. */
     // NOTE: This resolves UInt(width = 32)
-    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(width.W)
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
-    def apply(value: BigInt): UInt = apply(value, Width())
+    def apply(value: BigInt): UInt = value.asUInt
+
     /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
-    def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
+    def apply(dir: Direction, width: Int): UInt = apply(dir, width.W)
     /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
     def apply(dir: Direction): UInt = apply(dir, Width())
-    def apply(dir: Direction, wWidth: Width): UInt = {
-      val result = apply(wWidth)
+    def apply(dir: Direction, width: Width): UInt = {
+      val result = apply(width)
       dir match {
         case chisel3.core.Direction.Input => chisel3.core.Input(result)
         case chisel3.core.Direction.Output => chisel3.core.Output(result)
@@ -76,7 +75,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
     }
 
     /** Create a UInt with a specified width */
-    def width(width: Int): UInt = apply(Width(width))
+    def width(width: Int): UInt = apply(width.W)
 
     /** Create a UInt port with specified width. */
     def width(width: Width): UInt = apply(width)
@@ -86,29 +85,29 @@ package object Chisel {     // scalastyle:ignore package.object.name
     */
   trait SIntFactory extends chisel3.core.SIntFactory {
     /** Create a SInt type or port with fixed width. */
-    def width(width: Int): SInt = apply(Width(width))
+    def width(width: Int): SInt = apply(width.W)
     /** Create an SInt type with specified width. */
     def width(width: Width): SInt = apply(width)
 
     /** Create an SInt literal with inferred width. */
-    def apply(value: BigInt): SInt = Lit(value)
+    def apply(value: BigInt): SInt = value.S
     /** Create an SInt literal with fixed width. */
-    def apply(value: BigInt, width: Int): SInt = Lit(value, width)
+    def apply(value: BigInt, width: Int): SInt = value.S(width.W)
 
     /** Create an SInt literal with specified width. */
-    def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+    def apply(value: BigInt, width: Width): SInt = value.S(width)
 
-    def Lit(value: BigInt): SInt = Lit(value, Width())
-    def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
+    def Lit(value: BigInt): SInt = value.S
+    def Lit(value: BigInt, width: Int): SInt = value.S(width.W)
 
     /** Create a SInt with a specified width - compatibility with Chisel2. */
-    def apply(dir: Option[Direction] = None, width: Int): SInt = apply(Width(width))
+    def apply(dir: Option[Direction] = None, width: Int): SInt = apply(width.W)
     /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
-    def apply(dir: Direction, width: Int): SInt = apply(dir, Width(width))
+    def apply(dir: Direction, width: Int): SInt = apply(dir, width.W)
     /** Create a SInt with a specified direction, but unspecified width - compatibility with Chisel2. */
     def apply(dir: Direction): SInt = apply(dir, Width())
-    def apply(dir: Direction, wWidth: Width): SInt = {
-      val result = apply(wWidth)
+    def apply(dir: Direction, width: Width): SInt = {
+      val result = apply(width)
       dir match {
         case chisel3.core.Direction.Input => chisel3.core.Input(result)
         case chisel3.core.Direction.Output => chisel3.core.Output(result)
@@ -122,7 +121,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   trait BoolFactory extends chisel3.core.BoolFactory {
     /** Creates Bool literal.
      */
-    def apply(x: Boolean): Bool = Lit(x)
+    def apply(x: Boolean): Bool = x.B
 
     /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
     def apply(dir: Direction): Bool = {
@@ -175,6 +174,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val Driver = chisel3.Driver
   val ImplicitConversions = chisel3.util.ImplicitConversions
 
+  // Deprecated as of Chisel3
   object chiselMain {
     import java.io.File
 
@@ -194,6 +194,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
     def apply (arg: Data): Data = arg
   }
 
+  // Deprecated as of Chsiel3
   @throws(classOf[Exception])
   object throwException {
     def apply(s: String, t: Throwable = null) = {
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 5b02be34..326f8d7c 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -33,7 +33,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type Bits = chisel3.core.Bits
 
   /** This contains literal constructor factory methods that are deprecated as of Chisel3.
-    * These will be removed very soon. It's recommended you move your code soon.
+    * These will be removed very soon. It's recommended you port your code ASAP.
     *
     * Some recommended regex replacements:
     * (note: these are not guaranteed to handle all edge cases! check all replacements!)
@@ -48,32 +48,30 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
     @deprecated("use n.U", "chisel3, will be removed by end of 2016")
-    def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
-        chisel3.core.fromStringToLiteral.parsedWidth(n))
+    def apply(n: String): UInt = n.asUInt
     /** Create a UInt literal with fixed width. */
     @deprecated("use n.U(width.W)", "chisel3, will be removed by end of 2016")
-    def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
-        Width(width))
+    def apply(n: String, width: Int): UInt = n.asUInt(width.W)
 
     /** Create a UInt literal with specified width. */
     @deprecated("use value.U(width)", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt, width: Width): UInt = Lit(value, width)
+    def apply(value: BigInt, width: Width): UInt = value.asUInt(width)
 
     /** Create a UInt literal with fixed width. */
     @deprecated("use value.U(width.W)", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+    def apply(value: BigInt, width: Int): UInt = value.asUInt(width.W)
 
     /** Create a UInt with a specified width - compatibility with Chisel2. */
     @deprecated("use UInt(width.W)", "chisel3, will be removed by end of 2016")
-    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(width.W)
 
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
     @deprecated("use value.U", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt): UInt = apply(value, Width())
+    def apply(value: BigInt): UInt = value.asUInt
 
     /** Create a UInt with a specified width */
     @deprecated("use UInt(width.W)", "chisel3, will be removed by end of 2016")
-    def width(width: Int): UInt = apply(Width(width))
+    def width(width: Int): UInt = apply(width.W)
 
     /** Create a UInt port with specified width. */
     @deprecated("use UInt(width)", "chisel3, will be removed by end of 2016")
@@ -86,27 +84,27 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   trait SIntFactory extends chisel3.core.SIntFactory {
     /** Create a SInt type or port with fixed width. */
     @deprecated("use SInt(width.W)", "chisel3, will be removed by end of 2016")
-    def width(width: Int): SInt = apply(Width(width))
+    def width(width: Int): SInt = apply(width.W)
     /** Create an SInt type with specified width. */
     @deprecated("use SInt(width)", "chisel3, will be removed by end of 2016")
     def width(width: Width): SInt = apply(width)
 
     /** Create an SInt literal with inferred width. */
     @deprecated("use value.S", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt): SInt = Lit(value)
+    def apply(value: BigInt): SInt = value.asSInt
     /** Create an SInt literal with fixed width. */
     @deprecated("use value.S(width.W)", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt, width: Int): SInt = Lit(value, width)
+    def apply(value: BigInt, width: Int): SInt = value.asSInt(width.W)
 
     /** Create an SInt literal with specified width. */
     @deprecated("use value.S(width)", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+    def apply(value: BigInt, width: Width): SInt = value.asSInt(width)
 
     @deprecated("use value.S", "chisel3, will be removed by end of 2016")
-    def Lit(value: BigInt): SInt = Lit(value, Width())
+    def Lit(value: BigInt): SInt = value.asSInt
 
     @deprecated("use value.S(width)", "chisel3, will be removed by end of 2016")
-    def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
+    def Lit(value: BigInt, width: Int): SInt = value.asSInt(width.W)
   }
 
   /** This contains literal constructor factory methods that are deprecated as of Chisel3.
@@ -116,7 +114,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     /** Creates Bool literal.
      */
     @deprecated("use x.B", "chisel3, will be removed by end of 2016")
-    def apply(x: Boolean): Bool = Lit(x)
+    def apply(x: Boolean): Bool = x.B
   }
 
   object Bits extends UIntFactory
-- 
cgit v1.2.3


From a2b97f8dc9c261ae4dc39ea4e11feed7723e22dd Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:36:16 -0800
Subject: Restyle UInt->BitPatComparable

---
 src/main/scala/chisel3/package.scala | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 326f8d7c..7b07d964 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,10 +1,8 @@
 // See LICENSE for license details.
 
 package object chisel3 {    // scalastyle:ignore package.object.name
-  import scala.language.experimental.macros
+  import internal.firrtl.Width
 
-  import internal.firrtl.{Width, NumericBound}
-  import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
   import util.BitPat
 
   import chisel3.core.{Binding, FlippedBinder}
@@ -206,7 +204,10 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   implicit class fromDoubleToLiteral(override val x: Double) extends chisel3.core.fromDoubleToLiteral(x)
   implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
 
-  implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
+  implicit class fromUIntToBitPatComparable(val x: UInt) {
+    import scala.language.experimental.macros
+    import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3")
     final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
@@ -254,6 +255,9 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     implicit def fromStringToStringParam(x: String): StringParam = StringParam(x)
 
     implicit class ChiselRange(val sc: StringContext) extends AnyVal {
+      import scala.language.experimental.macros
+      import internal.firrtl.NumericBound
+
       /** Specifies a range using mathematical range notation. Variables can be interpolated using
        *  standard string interpolation syntax.
         * @example {{{
-- 
cgit v1.2.3


From ebe7a0fb5774ec4bec919f9d3acd987d084d91b4 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:50:50 -0800
Subject: better style

---
 src/main/scala/chisel3/compatibility.scala            | 10 +++++-----
 src/main/scala/chisel3/util/ImplicitConversions.scala |  2 ++
 2 files changed, 7 insertions(+), 5 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index fbe37f50..ff627c1e 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -90,15 +90,15 @@ package object Chisel {     // scalastyle:ignore package.object.name
     def width(width: Width): SInt = apply(width)
 
     /** Create an SInt literal with inferred width. */
-    def apply(value: BigInt): SInt = value.S
+    def apply(value: BigInt): SInt = value.asSInt
     /** Create an SInt literal with fixed width. */
-    def apply(value: BigInt, width: Int): SInt = value.S(width.W)
+    def apply(value: BigInt, width: Int): SInt = value.asSInt(width.W)
 
     /** Create an SInt literal with specified width. */
-    def apply(value: BigInt, width: Width): SInt = value.S(width)
+    def apply(value: BigInt, width: Width): SInt = value.asSInt(width)
 
-    def Lit(value: BigInt): SInt = value.S
-    def Lit(value: BigInt, width: Int): SInt = value.S(width.W)
+    def Lit(value: BigInt): SInt = value.asSInt
+    def Lit(value: BigInt, width: Int): SInt = value.asSInt(width.W)
 
     /** Create a SInt with a specified width - compatibility with Chisel2. */
     def apply(dir: Option[Direction] = None, width: Int): SInt = apply(width.W)
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 7f715ad4..c2ba710d 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -5,6 +5,8 @@ package chisel3.util
 import chisel3._
 
 object ImplicitConversions {
+  // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and
+  // UInt.asUInt.
   implicit def intToUInt(x: Int): UInt = chisel3.core.fromIntToLiteral(x).asUInt
   implicit def booleanToBool(x: Boolean): Bool = x.asBool
 }
-- 
cgit v1.2.3


From b50dbf2e17053d601213855642c117f429204fb8 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 14:40:31 -0800
Subject: Stop confusing scaladoc

---
 src/main/scala/chisel3/package.scala | 27 +++++++++++++++++----------
 1 file changed, 17 insertions(+), 10 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 7b07d964..50cb3dbe 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -30,18 +30,25 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
 
+  // Some possible regex replacements for the literal specifier deprecation:
+  // (note: these are not guaranteed to handle all edge cases! check all replacements!)
+  // Bool((true|false))
+  //  => $1.B
+  // UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\)
+  //  => UInt($1.W)
+  // (UInt|SInt|Bits).width\((\d+|[_a-zA-Z][_0-9a-zA-Z]*)\)
+  //  => $1($2.W)
+  // (U|S)Int\((-?\d+|0[xX][0-9a-fA-F]+)\)
+  //  => $2.$1
+  // UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\)
+  //  => $1.U($2.W)
+  // (UInt|SInt|Bool)\(([_a-zA-Z][_0-9a-zA-Z]*)\)
+  //  => $2.as$1
+  // (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\)
+  //  => $2.as$1($3.W)
+
   /** This contains literal constructor factory methods that are deprecated as of Chisel3.
     * These will be removed very soon. It's recommended you port your code ASAP.
-    *
-    * Some recommended regex replacements:
-    * (note: these are not guaranteed to handle all edge cases! check all replacements!)
-    * Bool((true|false)) => $1.B
-    * UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => UInt($1.W)
-    * (UInt|SInt|Bits).width\((\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $1($2.W)
-    * (U|S)Int\((-?\d+|0[xX][0-9a-fA-F]+)\) => $2.$1
-    * UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $1.U($2.W)
-    * (UInt|SInt|Bool)\(([_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1
-    * (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1($3.W)
     */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
-- 
cgit v1.2.3


From 75da1093142b57a58d61fe5e57181041bc59146d Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 15:37:20 -0800
Subject: Fix regex example

---
 src/main/scala/chisel3/package.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 50cb3dbe..44d1f6c1 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -32,7 +32,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
 
   // Some possible regex replacements for the literal specifier deprecation:
   // (note: these are not guaranteed to handle all edge cases! check all replacements!)
-  // Bool((true|false))
+  // Bool\((true|false)\)
   //  => $1.B
   // UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\)
   //  => UInt($1.W)
-- 
cgit v1.2.3


From 6b7acc715010b14c22e15f5084efb11862151a47 Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 18 Nov 2016 12:50:35 -0800
Subject: Fix Log2

---
 src/main/scala/chisel3/util/CircuitMath.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 83e5feb1..a422b5fe 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -18,7 +18,7 @@ object Log2 {
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), UInt((width-1).W), apply(x, width-1))
+      Mux(x(width-1), (width-1).asUInt, apply(x, width-1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
       val hi = x(width-1, mid)
-- 
cgit v1.2.3


From 81e5d00d18a5ba9ae33c10219a270148002fc672 Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 18 Nov 2016 13:36:03 -0800
Subject: Deboilerplate the implicit conversions, add support for long.U

---
 src/main/scala/chisel3/compatibility.scala | 11 ++++++-----
 src/main/scala/chisel3/package.scala       | 13 +++++++------
 2 files changed, 13 insertions(+), 11 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index ff627c1e..51176d9d 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -164,11 +164,12 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val when = chisel3.core.when
   type WhenContext = chisel3.core.WhenContext
 
-  implicit class fromtIntToLiteral(override val x: Int) extends chisel3.core.fromIntToLiteral(x)
-  implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
-  implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
-  implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
-  implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
+  implicit class fromBigIntToLiteral(val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
+  implicit class fromtIntToLiteral(val x: Int) extends chisel3.core.fromIntToLiteral(x)
+  implicit class fromtLongToLiteral(val x: Long) extends chisel3.core.fromLongToLiteral(x)
+  implicit class fromStringToLiteral(val x: String) extends chisel3.core.fromStringToLiteral(x)
+  implicit class fromBooleanToLiteral(val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
+  implicit class fromIntToWidth(val x: Int) extends chisel3.core.fromIntToWidth(x)
 
   type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
   val Driver = chisel3.Driver
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 44d1f6c1..449f4ea5 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -204,12 +204,13 @@ package object chisel3 {    // scalastyle:ignore package.object.name
 
   implicit def string2Printable(str: String): Printable = PString(str)
 
-  implicit class fromtIntToLiteral(override val x: Int) extends chisel3.core.fromIntToLiteral(x)
-  implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
-  implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
-  implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
-  implicit class fromDoubleToLiteral(override val x: Double) extends chisel3.core.fromDoubleToLiteral(x)
-  implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
+  implicit class fromBigIntToLiteral(val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
+  implicit class fromtIntToLiteral(val x: Int) extends chisel3.core.fromIntToLiteral(x)
+  implicit class fromtLongToLiteral(val x: Long) extends chisel3.core.fromLongToLiteral(x)
+  implicit class fromStringToLiteral(val x: String) extends chisel3.core.fromStringToLiteral(x)
+  implicit class fromBooleanToLiteral(val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
+  implicit class fromDoubleToLiteral(val x: Double) extends chisel3.core.fromDoubleToLiteral(x)
+  implicit class fromIntToWidth(val x: Int) extends chisel3.core.fromIntToWidth(x)
 
   implicit class fromUIntToBitPatComparable(val x: UInt) {
     import scala.language.experimental.macros
-- 
cgit v1.2.3


From 11302f77c90512f81b882ad1cc623c53d45724f8 Mon Sep 17 00:00:00 2001
From: Donggyu
Date: Mon, 21 Nov 2016 14:52:05 -0800
Subject: Remove deduplication from Chisel (#347)

Remove modName from Module---
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 20 +++++---------------
 1 file changed, 5 insertions(+), 15 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index b8651828..42bc6c30 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -32,7 +32,7 @@ private class Emitter(circuit: Circuit) {
           "\"" + printf.format(fmt) + "\"") ++ args
         printfArgs mkString ("printf(", ", ", ")")
       case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"
-      case e: DefInstance => s"inst ${e.name} of ${e.id.modName}"
+      case e: DefInstance => s"inst ${e.name} of ${e.id.name}"
       case w: WhenBegin =>
         indent()
         s"when ${w.pred.fullName(ctx)} :"
@@ -53,9 +53,6 @@ private class Emitter(circuit: Circuit) {
     s"parameter $name = $str"
   }
 
-  // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already.
-  private val defnMap = collection.mutable.HashMap[(String, String), Component]()
-
   /** Generates the FIRRTL module declaration.
     */
   private def moduleDecl(m: Component): String = m.id match {
@@ -92,17 +89,10 @@ private class Emitter(circuit: Circuit) {
     */
   private def emit(m: Component): String = {
     // Generate the body.
-    val defn = moduleDefn(m)
-
-    defnMap get (m.id.desiredName, defn) match {
-      case Some(duplicate) =>
-        m.id setModName duplicate.name
-        ""
-      case None =>
-        defnMap((m.id.desiredName, defn)) = m
-        m.id setModName m.name
-        moduleDecl(m) + defn
-    }
+    val sb = new StringBuilder
+    sb.append(moduleDecl(m))
+    sb.append(moduleDefn(m))
+    sb.result
   }
 
   private var indentLevel = 0
-- 
cgit v1.2.3


From edb19a0559686a471141c74438f677c1e217a298 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Wed, 23 Nov 2016 16:01:50 -0800
Subject: Simplify Enum API (#385)

Get rid of some cruft exposed in #373

This also allows Bits.fromtInt(...) to be removed. Yay!

All old APIs (with some new restrictions, rocket still works fine) are preserved without deprecation in Chisel._, aside from the non-compile-time-checkable Map[] enum constructor which probably should have been deprecated during chisel2. The Map[] enums have been removed from chisel3._ without deprecation.

The new restriction is that nodeType (legacy API) may only be of UInt type with unspecified width. Note that Bits() creates a UInt, and if you can't control the enum values, it makes little sense to specify a bitwidth.---
 src/main/scala/chisel3/compatibility.scala | 57 +++++++++++++++++++++++++++++-
 src/main/scala/chisel3/util/Enum.scala     | 41 ++++++++-------------
 2 files changed, 70 insertions(+), 28 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 51176d9d..4ffd0b86 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -250,7 +250,62 @@ package object Chisel {     // scalastyle:ignore package.object.name
   type Queue[T <: Data] = chisel3.util.Queue[T]
   val Queue = chisel3.util.Queue
 
-  val Enum = chisel3.util.Enum
+  object Enum extends chisel3.util.Enum {
+    /** Returns n unique values of the specified type. Can be used with unpacking to define enums.
+      *
+      * nodeType must be of UInt type (note that Bits() creates a UInt) with unspecified width.
+      *
+      * @example {{{
+      * val state_on :: state_off :: Nil = Enum(UInt(), 2)
+      * val current_state = UInt()
+      * switch (current_state) {
+      *   is (state_on) {
+      *      ...
+      *   }
+      *   if (state_off) {
+      *      ...
+      *   }
+      * }
+      * }}}
+      */
+    def apply[T <: Bits](nodeType: T, n: Int): List[T] = {
+      require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
+      require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
+      apply(n).asInstanceOf[List[T]]
+    }
+
+    /** An old Enum API that returns a map of symbols to UInts.
+      *
+      * Unlike the new list-based Enum, which can be unpacked into vals that the compiler
+      * understands and can check, map accesses can't be compile-time checked and typos may not be
+      * caught until runtime.
+      *
+      * Despite being deprecated, this is not to be removed from the compatibility layer API.
+      * Deprecation is only to nag users to do something safer.
+      */
+    @deprecated("Use list-based Enum", "not soon enough")
+    def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = {
+      require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
+      require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
+      (l zip createValues(l.length)).toMap.asInstanceOf[Map[Symbol, T]]
+    }
+
+    /** An old Enum API that returns a map of symbols to UInts.
+      *
+      * Unlike the new list-based Enum, which can be unpacked into vals that the compiler
+      * understands and can check, map accesses can't be compile-time checked and typos may not be
+      * caught until runtime.
+      *
+      * Despite being deprecated, this is not to be removed from the compatibility layer API.
+      * Deprecation is only to nag users to do something safer.
+      */
+    @deprecated("Use list-based Enum", "not soon enough")
+    def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = {
+      require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
+      require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
+      (l zip createValues(l.length)).toMap.asInstanceOf[Map[Symbol, T]]
+    }
+  }
 
   val LFSR16 = chisel3.util.LFSR16
 
diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala
index 55b595ee..45aee62a 100644
--- a/src/main/scala/chisel3/util/Enum.scala
+++ b/src/main/scala/chisel3/util/Enum.scala
@@ -7,15 +7,15 @@ package chisel3.util
 
 import chisel3._
 
-object Enum {
+trait Enum {
   /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
-  private def createValues[T <: Bits](nodeType: T, n: Int): Seq[T] =
-    (0 until n).map(x => nodeType.fromInt(x, log2Up(n)))
+  protected def createValues(n: Int): Seq[UInt] =
+    (0 until n).map(_.U(log2Up(n).W))
 
-  /** Returns n unique values of the specified type. Can be used with unpacking to define enums.
+  /** Returns n unique UInt values, use with unpacking to specify an enumeration.
     *
     * @example {{{
-    * val state_on :: state_off :: Nil = Enum(UInt(), 2)
+    * val state_on :: state_off :: Nil = Enum(2)
     * val current_state = UInt()
     * switch (current_state) {
     *   is (state_on) {
@@ -26,28 +26,15 @@ object Enum {
     *   }
     * }
     * }}}
-    *
     */
-  def apply[T <: Bits](nodeType: T, n: Int): List[T] = createValues(nodeType, n).toList
-
-  /** Returns a map of the input symbols to unique values of the specified type.
-    *
-    * @example {{{
-    * val states = Enum(UInt(), 'on, 'off)
-    * val current_state = UInt()
-    * switch (current_state) {
-    *   is (states('on)) {
-    *     ...
-    *   }
-    *   if (states('off)) {
-    *     ..
-    *   }
-    * }
-    * }}}
-    */
-  def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap
+  def apply(n: Int): List[UInt] = createValues(n).toList
+}
 
-  /** Returns a map of the input symbols to unique values of the specified type.
-    */
-  def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap
+object Enum extends Enum {
+  @deprecated("use Enum(n)", "chisel3, will be removed soon")
+  def apply[T <: Bits](nodeType: T, n: Int): List[T] = {
+    require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
+    require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
+    apply(n).asInstanceOf[List[T]]
+  }
 }
-- 
cgit v1.2.3


From 7680363982b02f53e9f76f5d5e242e44f17da6f7 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Tue, 29 Nov 2016 16:37:13 -0800
Subject: Add feature warnings to build, fix feature warnings, fix some
 documentation (#387)

---
 src/main/scala/chisel3/compatibility.scala            | 2 +-
 src/main/scala/chisel3/package.scala                  | 8 +++++---
 src/main/scala/chisel3/testers/TesterDriver.scala     | 2 +-
 src/main/scala/chisel3/util/ImplicitConversions.scala | 2 ++
 src/main/scala/chisel3/util/Valid.scala               | 6 ++++--
 5 files changed, 13 insertions(+), 7 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 4ffd0b86..613385af 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -120,7 +120,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
     */
   trait BoolFactory extends chisel3.core.BoolFactory {
     /** Creates Bool literal.
-     */
+      */
     def apply(x: Boolean): Bool = x.B
 
     /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 449f4ea5..e4e64b89 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
 package object chisel3 {    // scalastyle:ignore package.object.name
+  import scala.language.implicitConversions
+
   import internal.firrtl.Width
 
   import util.BitPat
@@ -267,11 +269,11 @@ package object chisel3 {    // scalastyle:ignore package.object.name
       import internal.firrtl.NumericBound
 
       /** Specifies a range using mathematical range notation. Variables can be interpolated using
-       *  standard string interpolation syntax.
+        * standard string interpolation syntax.
         * @example {{{
         * UInt(range"[0, 2)")
-        * UInt(range"[0, $myInt)")
-        * UInt(range"[0, ${myInt + 2})")
+        * UInt(range"[0, \$myInt)")
+        * UInt(range"[0, \${myInt + 2})")
         * }}}
         */
       def range(args: Any*): (NumericBound[Int], NumericBound[Int]) = macro chisel3.internal.RangeTransform.apply
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index 76b9a2e9..83f3c796 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -14,7 +14,7 @@ object TesterDriver extends BackendCompilationUtilities {
       throw new FileNotFoundException(s"Resource '$name'")
     }
     val out = new FileOutputStream(file)
-    Iterator.continually(in.read).takeWhile(-1 !=).foreach(out.write)
+    Iterator.continually(in.read).takeWhile(-1 != _).foreach(out.write)
     out.close()
   }
 
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index c2ba710d..712975a7 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -4,6 +4,8 @@ package chisel3.util
 
 import chisel3._
 
+import scala.language.implicitConversions
+
 object ImplicitConversions {
   // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and
   // UInt.asUInt.
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 49a6f515..0229b7f8 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -52,10 +52,12 @@ object Pipe
 
 class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module
 {
-  val io = IO(new Bundle {
+  class PipeIO extends Bundle {
     val enq = Input(Valid(gen))
     val deq = Output(Valid(gen))
-  })
+  }
+
+  val io = IO(new PipeIO)
 
   io.deq <> Pipe(io.enq, latency)
 }
-- 
cgit v1.2.3


From 9aba55e7452981058d069b3096544d45e730dba9 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Tue, 6 Dec 2016 17:16:40 -0800
Subject: utils scaladoc examples for BitPat through CircuitMath (#398)

Add examples for utils, move examples from individual apply methods to class overview scaladoc---
 src/main/scala/chisel3/util/BitPat.scala      | 19 ++++++++---
 src/main/scala/chisel3/util/Bitwise.scala     | 46 +++++++++++++++++++++++----
 src/main/scala/chisel3/util/Cat.scala         | 13 +++++++-
 src/main/scala/chisel3/util/CircuitMath.scala | 17 ++++++----
 4 files changed, 77 insertions(+), 18 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 9c9909cd..add40f79 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -35,7 +35,7 @@ object BitPat {
   }
 
   /** Creates a [[BitPat]] literal from a string.
-   *
+    *
     * @param n the literal value as a string, in binary, prefixed with 'b'
     * @note legal characters are '0', '1', and '?', as well as '_' and white
     * space (which are ignored)
@@ -45,7 +45,12 @@ object BitPat {
     new BitPat(bits, mask, width)
   }
 
-  /** Creates a [[BitPat]] of all don't cares of the specified bitwidth. */
+  /** Creates a [[BitPat]] of all don't cares of the specified bitwidth.
+    *
+    * @example {{{
+    * val myDontCare = BitPat.dontCare(4)  // equivalent to BitPat("b????")
+    * }}}
+    */
   def dontCare(width: Int): BitPat = BitPat("b" + ("?" * width))
 
   @deprecated("Use BitPat.dontCare", "chisel3")
@@ -73,10 +78,14 @@ object BitPat {
   }
 }
 
-// TODO: Break out of Core? (this doesn't involve FIRRTL generation)
 /** Bit patterns are literals with masks, used to represent values with don't
-  * cares. Equality comparisons will ignore don't care bits (for example,
-  * BitPat(0b10?1) === 0b1001.asUInt and 0b1011.asUInt.
+  * care bits. Equality comparisons will ignore don't care bits.
+  *
+  * @example {{{
+  * "b10101".U === BitPat("b101??") // evaluates to true.B
+  * "b10111".U === BitPat("b101??") // evaluates to true.B
+  * "b10001".U === BitPat("b101??") // evaluates to false.B
+  * }}}
   */
 sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
   def getWidth: Int = width
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 22326972..950fa65f 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -8,11 +8,21 @@ package chisel3.util
 import chisel3._
 import chisel3.core.SeqUtils
 
+/** Creates repetitions of each bit of the input in order.
+  *
+  * @example {{{
+  * FillInterleaved(2, "b1 0 0 0".U)  // equivalent to "b11 00 00 00".U
+  * FillInterleaved(2, "b1 0 0 1".U)  // equivalent to "b11 00 00 11".U
+  * FillInterleaved(2, myUIntWire)  // dynamic interleaved fill
+  *
+  * FillInterleaved(2, Seq(true.B, false.B, false.B, false.B))  // equivalent to "b11 00 00 00".U
+  * FillInterleaved(2, Seq(true.B, false.B, false.B, true.B))  // equivalent to "b11 00 00 11".U
+  * }}}
+  */
 object FillInterleaved {
   /** Creates n repetitions of each bit of x in order.
     *
     * Output data-equivalent to in(size(in)-1) (n times) ## ... ## in(1) (n times) ## in(0) (n times)
-    * For example, FillInterleaved(2, "b1000") === UInt("b11 00 00 00")
     */
   def apply(n: Int, in: UInt): UInt = apply(n, in.toBools)
 
@@ -23,14 +33,31 @@ object FillInterleaved {
   def apply(n: Int, in: Seq[Bool]): UInt = Cat(in.map(Fill(n, _)).reverse)
 }
 
-/** Returns the number of bits set (i.e value is 1) in the input signal.
+/** Returns the number of bits set (value is 1 or true) in the input signal.
+  *
+  * @example {{{
+  * PopCount(Seq(true.B, false.B, true.B, true.B))  // evaluates to 3.U
+  * PopCount(Seq(false.B, false.B, true.B, false.B))  // evaluates to 1.U
+  *
+  * PopCount("b1011".U)  // evaluates to 3.U
+  * PopCount("b0010".U)  // evaluates to 1.U
+  * PopCount(myUIntWire)  // dynamic count
+  * }}}
   */
-object PopCount
-{
+object PopCount {
   def apply(in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq)
+
   def apply(in: Bits): UInt = apply((0 until in.getWidth).map(in(_)))
 }
 
+/** Create repetitions of the input using a tree fanout topology.
+  *
+  * @example {{{
+  * Fill(2, "b1000".U)  // equivalent to "b1000 1000".U
+  * Fill(2, "b1001".U)  // equivalent to "b1001 1001".U
+  * Fill(2, myUIntWire)  // dynamic fill
+  * }}}
+  */
 object Fill {
   /** Create n repetitions of x using a tree fanout topology.
     *
@@ -53,6 +80,14 @@ object Fill {
   }
 }
 
+/** Returns the input in bit-reversed order. Useful for little/big-endian conversion.
+  *
+  * @example {{{
+  * Reverse("b1101".U)  // equivalent to "b1011".U
+  * Reverse("b1101".U(8.W))  // equivalent to "b10110000".U
+  * Reverse(myUIntWire)  // dynamic reverse
+  * }}}
+  */
 object Reverse {
   private def doit(in: UInt, length: Int): UInt = {
     if (length == 1) {
@@ -73,7 +108,6 @@ object Reverse {
       Cat(doit(in(half-1,0), half), doit(in(length-1,half), length-half))
     }
   }
-  /** Returns the input in bit-reversed order. Useful for little/big-endian conversion.
-    */
+
   def apply(in: UInt): UInt = doit(in, in.getWidth)
 }
diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala
index ba12a7d4..78801541 100644
--- a/src/main/scala/chisel3/util/Cat.scala
+++ b/src/main/scala/chisel3/util/Cat.scala
@@ -5,8 +5,19 @@ package chisel3.util
 import chisel3._
 import chisel3.core.SeqUtils
 
+/** Concatenates elements of the input, in order, together.
+  *
+  * @example {{{
+  * Cat("b101".U, "b11".U)  // equivalent to "b101 11".U
+  * Cat(myUIntWire0, myUIntWire1)
+  *
+  * Cat(Seq("b101".U, "b11".U))  // equivalent to "b101 11".U
+  * Cat(mySeqOfBits)
+  * }}}
+  */
 object Cat {
-  /** Concatenates the argument data elements, in argument order, together.
+  /** Concatenates the argument data elements, in argument order, together. The first argument
+    * forms the most significant bits, while the last argument forms the least significant bits.
     */
   def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList)
 
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index a422b5fe..b5f491ef 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -7,10 +7,19 @@ package chisel3.util
 
 import chisel3._
 
+/** Returns the base-2 integer logarithm of an UInt.
+  *
+  * @note The result is truncated, so e.g. Log2(13.U) === 3.U
+  *
+  * @example {{{
+  * Log2(8.U)  // evaluates to 3.U
+  * Log2(13.U)  // evaluates to 3.U (truncation)
+  * Log2(myUIntWire)
+  * }}}
+  *
+  */
 object Log2 {
   /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
-    *
-    * @note The result is truncated, so e.g. Log2(13.U) === 3.U
     */
   def apply(x: Bits, width: Int): UInt = {
     if (width < 2) {
@@ -28,10 +37,6 @@ object Log2 {
     }
   }
 
-  /** Returns the base-2 integer logarithm of an UInt.
-    *
-    * @note The result is truncated, so e.g. Log2(13.U) === 3.U
-    */
   def apply(x: Bits): UInt = apply(x, x.getWidth)
 
   private def divideAndConquerThreshold = 4
-- 
cgit v1.2.3


From ad53161bbb9f67e16b88ca7a508a537f88d77e05 Mon Sep 17 00:00:00 2001
From: Chick Markley
Date: Wed, 7 Dec 2016 10:31:23 -0800
Subject: Support for creating chisel annotations that are consumed by firrtl
 (#393)

* Support for creating chisel annotations that are consumed by firrtl
Update annotation serialization in Driver
Add DiamondAnnotation Spec that illustrates how to do simple annotations
frontEnd must have dependency on firrtl
Add annotation method to Module
Circuit has extra optional parameter that is Seq of Annotations
In Builder add annotation buffer to DynamicContext to store annotations created in modules
Added explicit types on naming api methods to avoid type confusion
Because some names are not available until elaboration create intermediate ChiselAnnotation that
gets turned into a firrtl Annotation after elaboration
In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though
intermediate file .fir and .anno files are still created for inspection and/or later use

* Somehow missed ChiselAnnotation

* fixes for Jack's review of PR
---
 src/main/scala/chisel3/Driver.scala  | 12 ++++++++++++
 src/main/scala/chisel3/package.scala |  3 +++
 2 files changed, 15 insertions(+)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index ab51ad25..646702c3 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -6,10 +6,13 @@ import chisel3.internal.firrtl.Emitter
 
 import scala.sys.process._
 import java.io._
+import net.jcazevedo.moultingyaml._
 
 import internal.firrtl._
 import firrtl._
 
+import _root_.firrtl.annotations.AnnotationYamlProtocol._
+
 /**
   * The Driver provides methods to invoke the chisel3 compiler and the firrtl compiler.
   * By default firrtl is automatically run after chisel.  an [[ExecutionOptionsManager]]
@@ -239,6 +242,15 @@ object Driver extends BackendCompilationUtilities {
     w.write(firrtlString)
     w.close()
 
+    val annotationFile = new File(optionsManager.getBuildFileName("anno"))
+    val af = new FileWriter(annotationFile)
+    af.write(circuit.annotations.toArray.toYaml.prettyPrint)
+    af.close()
+
+    /* This passes the firrtl source and annotations directly to firrtl */
+    optionsManager.firrtlOptions = optionsManager.firrtlOptions.copy(
+      firrtlSource = Some(firrtlString), annotations = circuit.annotations.toList)
+
     val firrtlExecutionResult = if(chiselOptions.runFirrtlCompiler) {
       Some(firrtl.Driver.execute(optionsManager))
     }
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index e4e64b89..25d3ec3a 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -32,6 +32,9 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
 
+  type ChiselAnnotation = chisel3.core.ChiselAnnotation
+  val ChiselAnnotation = chisel3.core.ChiselAnnotation
+
   // Some possible regex replacements for the literal specifier deprecation:
   // (note: these are not guaranteed to handle all edge cases! check all replacements!)
   // Bool\((true|false)\)
-- 
cgit v1.2.3