From a3ddd4b98049b624080422717c6822ec9ab43e07 Mon Sep 17 00:00:00 2001
From: Martin Schoeberl
Date: Wed, 16 Jun 2021 19:33:26 +0200
Subject: getVerilog in Chisel3 (#1921)

---
 src/main/scala/chisel3/verilog.scala | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 src/main/scala/chisel3/verilog.scala

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/verilog.scala b/src/main/scala/chisel3/verilog.scala
new file mode 100644
index 00000000..a91444de
--- /dev/null
+++ b/src/main/scala/chisel3/verilog.scala
@@ -0,0 +1,15 @@
+package chisel3
+
+import chisel3.stage.ChiselStage
+import firrtl.AnnotationSeq
+
+object getVerilogString {
+  def apply(gen: => RawModule): String = ChiselStage.emitVerilog(gen)
+}
+
+object emitVerilog {
+  def apply(gen: => RawModule, args: Array[String] = Array.empty,
+                  annotations: AnnotationSeq = Seq.empty): Unit = {
+    (new ChiselStage).emitVerilog(gen, args, annotations)
+  }
+}
-- 
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