From a3cd76901958ee88da2b56d67ce0dee263d3301c Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Thu, 30 Jul 2015 17:42:25 -0700
Subject: Correct implementation of andR

---
 src/main/scala/Chisel/Core.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index d054c10f..27d07e30 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -668,8 +668,8 @@ sealed abstract class Bits(dirArg: Direction, width: Int, lit: Option[LitArg]) e
     d
   }
 
-  def orR = !(this === Bits(0))
-  def andR = (this === Bits(-1))
+  def orR = this != Bits(0)
+  def andR = ~this === Bits(0)
   def xorR = bits_redop(XorReduceOp)
 
   def toBools: Vec[Bool] = Vec.tabulate(this.getWidth)(i => this(i))
-- 
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