From 8baa2ab806be1aa85a7a1da7b348726da1bd1d19 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 11 May 2017 15:07:30 -0700 Subject: Scope resources - move them down into chisel3 directory - fixes #549 (#610) --- src/main/resources/Makefile | 35 --------- src/main/resources/chisel3/Makefile | 35 +++++++++ src/main/resources/chisel3/top.cpp | 95 +++++++++++++++++++++++ src/main/resources/top.cpp | 95 ----------------------- src/main/scala/chisel3/testers/TesterDriver.scala | 2 +- 5 files changed, 131 insertions(+), 131 deletions(-) delete mode 100644 src/main/resources/Makefile create mode 100644 src/main/resources/chisel3/Makefile create mode 100644 src/main/resources/chisel3/top.cpp delete mode 100644 src/main/resources/top.cpp (limited to 'src/main') diff --git a/src/main/resources/Makefile b/src/main/resources/Makefile deleted file mode 100644 index 221179a3..00000000 --- a/src/main/resources/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -# Chisel parallel make template. - -HFILES = @HFILES@ -ONCEONLY = @ONCEONLY@ -UNOPTIMIZED = @UNOPTIMIZED@ -OPTIMIZED = @OPTIMIZED@ - -EXEC = @EXEC@ -OPTIM0 = @OPTIM0@ -OPTIM1 = @OPTIM1@ -OPTIM2 = @OPTIM2@ -CPPFLAGS = @CPPFLAGS@ -CXXFLAGS = @CXXFLAGS@ -LDFLAGS = @LDFLAGS@ -CXX = @CXX@ - -default: $(EXEC) - -clean: - $(RM) $(EXEC) $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) - -$(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED): $(HFILES) - -$(EXEC): $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) Makefile - $(CXX) -o $@ $(filter-out Makefile,$^) - -$(ONCEONLY): %.o: %.cpp - $(CXX) -c -o $@ $(OPTIM0) $(CPPFLAGS) $(CXXFLAGS) $< - -$(UNOPTIMIZED): %.o: %.cpp - $(CXX) -c -o $@ $(OPTIM1) $(CPPFLAGS) $(CXXFLAGS) $< - -$(OPTIMIZED): %.o: %.cpp - $(CXX) -c -o $@ $(OPTIM2) $(CPPFLAGS) $(CXXFLAGS) $< - \ No newline at end of file diff --git a/src/main/resources/chisel3/Makefile b/src/main/resources/chisel3/Makefile new file mode 100644 index 00000000..221179a3 --- /dev/null +++ b/src/main/resources/chisel3/Makefile @@ -0,0 +1,35 @@ +# Chisel parallel make template. + +HFILES = @HFILES@ +ONCEONLY = @ONCEONLY@ +UNOPTIMIZED = @UNOPTIMIZED@ +OPTIMIZED = @OPTIMIZED@ + +EXEC = @EXEC@ +OPTIM0 = @OPTIM0@ +OPTIM1 = @OPTIM1@ +OPTIM2 = @OPTIM2@ +CPPFLAGS = @CPPFLAGS@ +CXXFLAGS = @CXXFLAGS@ +LDFLAGS = @LDFLAGS@ +CXX = @CXX@ + +default: $(EXEC) + +clean: + $(RM) $(EXEC) $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) + +$(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED): $(HFILES) + +$(EXEC): $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) Makefile + $(CXX) -o $@ $(filter-out Makefile,$^) + +$(ONCEONLY): %.o: %.cpp + $(CXX) -c -o $@ $(OPTIM0) $(CPPFLAGS) $(CXXFLAGS) $< + +$(UNOPTIMIZED): %.o: %.cpp + $(CXX) -c -o $@ $(OPTIM1) $(CPPFLAGS) $(CXXFLAGS) $< + +$(OPTIMIZED): %.o: %.cpp + $(CXX) -c -o $@ $(OPTIM2) $(CPPFLAGS) $(CXXFLAGS) $< + \ No newline at end of file diff --git a/src/main/resources/chisel3/top.cpp b/src/main/resources/chisel3/top.cpp new file mode 100644 index 00000000..4e9c1433 --- /dev/null +++ b/src/main/resources/chisel3/top.cpp @@ -0,0 +1,95 @@ +#include +#include + +#if VM_TRACE +# include // Trace file format header +#endif + +// Override Verilator definition so first $finish ends simulation +// Note: VL_USER_FINISH needs to be defined when compiling Verilator code +void vl_finish(const char* filename, int linenum, const char* hier) { + Verilated::flushCall(); + exit(0); +} + +using namespace std; + +//VGCDTester *top; +TOP_TYPE *top; + +vluint64_t main_time = 0; // Current simulation time + // This is a 64-bit integer to reduce wrap over issues and + // allow modulus. You can also use a double, if you wish. + +double sc_time_stamp () { // Called by $time in Verilog + return main_time; // converts to double, to match + // what SystemC does +} + +// TODO Provide command-line options like vcd filename, timeout count, etc. +const long timeout = 100000000L; + +int main(int argc, char** argv) { + Verilated::commandArgs(argc, argv); // Remember args + top = new TOP_TYPE; + +#if VM_TRACE // If verilator was invoked with --trace + Verilated::traceEverOn(true); // Verilator must compute traced signals + VL_PRINTF("Enabling waves...\n"); + VerilatedVcdC* tfp = new VerilatedVcdC; + top->trace (tfp, 99); // Trace 99 levels of hierarchy + tfp->open ("dump.vcd"); // Open the dump file +#endif + + + top->reset = 1; + + cout << "Starting simulation!\n"; + + while (!Verilated::gotFinish() && main_time < timeout) { + if (main_time > 10) { + top->reset = 0; // Deassert reset + } + if ((main_time % 10) == 1) { + top->clock = 1; // Toggle clock + } + if ((main_time % 10) == 6) { + top->clock = 0; + } + top->eval(); // Evaluate model +#if VM_TRACE + if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp +#endif + main_time++; // Time passes... + } + + if (main_time >= timeout) { + cout << "Simulation terminated by timeout at time " << main_time << + " (cycle " << main_time / 10 << ")"<< endl; + return -1; + } else { + cout << "Simulation completed at time " << main_time << + " (cycle " << main_time / 10 << ")"<< endl; + } + + // Run for 10 more clocks + vluint64_t end_time = main_time + 100; + while (main_time < end_time) { + if ((main_time % 10) == 1) { + top->clock = 1; // Toggle clock + } + if ((main_time % 10) == 6) { + top->clock = 0; + } + top->eval(); // Evaluate model +#if VM_TRACE + if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp +#endif + main_time++; // Time passes... + } + +#if VM_TRACE + if (tfp) tfp->close(); +#endif +} + diff --git a/src/main/resources/top.cpp b/src/main/resources/top.cpp deleted file mode 100644 index 4e9c1433..00000000 --- a/src/main/resources/top.cpp +++ /dev/null @@ -1,95 +0,0 @@ -#include -#include - -#if VM_TRACE -# include // Trace file format header -#endif - -// Override Verilator definition so first $finish ends simulation -// Note: VL_USER_FINISH needs to be defined when compiling Verilator code -void vl_finish(const char* filename, int linenum, const char* hier) { - Verilated::flushCall(); - exit(0); -} - -using namespace std; - -//VGCDTester *top; -TOP_TYPE *top; - -vluint64_t main_time = 0; // Current simulation time - // This is a 64-bit integer to reduce wrap over issues and - // allow modulus. You can also use a double, if you wish. - -double sc_time_stamp () { // Called by $time in Verilog - return main_time; // converts to double, to match - // what SystemC does -} - -// TODO Provide command-line options like vcd filename, timeout count, etc. -const long timeout = 100000000L; - -int main(int argc, char** argv) { - Verilated::commandArgs(argc, argv); // Remember args - top = new TOP_TYPE; - -#if VM_TRACE // If verilator was invoked with --trace - Verilated::traceEverOn(true); // Verilator must compute traced signals - VL_PRINTF("Enabling waves...\n"); - VerilatedVcdC* tfp = new VerilatedVcdC; - top->trace (tfp, 99); // Trace 99 levels of hierarchy - tfp->open ("dump.vcd"); // Open the dump file -#endif - - - top->reset = 1; - - cout << "Starting simulation!\n"; - - while (!Verilated::gotFinish() && main_time < timeout) { - if (main_time > 10) { - top->reset = 0; // Deassert reset - } - if ((main_time % 10) == 1) { - top->clock = 1; // Toggle clock - } - if ((main_time % 10) == 6) { - top->clock = 0; - } - top->eval(); // Evaluate model -#if VM_TRACE - if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp -#endif - main_time++; // Time passes... - } - - if (main_time >= timeout) { - cout << "Simulation terminated by timeout at time " << main_time << - " (cycle " << main_time / 10 << ")"<< endl; - return -1; - } else { - cout << "Simulation completed at time " << main_time << - " (cycle " << main_time / 10 << ")"<< endl; - } - - // Run for 10 more clocks - vluint64_t end_time = main_time + 100; - while (main_time < end_time) { - if ((main_time % 10) == 1) { - top->clock = 1; // Toggle clock - } - if ((main_time % 10) == 6) { - top->clock = 0; - } - top->eval(); // Evaluate model -#if VM_TRACE - if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp -#endif - main_time++; // Time passes... - } - -#if VM_TRACE - if (tfp) tfp->close(); -#endif -} - diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala index fd3ad9ba..fc71f2b0 100644 --- a/src/main/scala/chisel3/testers/TesterDriver.scala +++ b/src/main/scala/chisel3/testers/TesterDriver.scala @@ -28,7 +28,7 @@ object TesterDriver extends BackendCompilationUtilities { // Copy CPP harness and other Verilog sources from resources into files val cppHarness = new File(path, "top.cpp") - copyResourceToFile("/top.cpp", cppHarness) + copyResourceToFile("/chisel3/top.cpp", cppHarness) val additionalVFiles = additionalVResources.map((name: String) => { val mangledResourceName = name.replace("/", "_") val out = new File(path, mangledResourceName) -- cgit v1.2.3