From 632a7166ac1935100cb1d61add3b28d1fd4dc8f4 Mon Sep 17 00:00:00 2001
From: Chick Markley
Date: Tue, 31 Jan 2017 09:49:18 -0800
Subject: Move blackbox verilog implementations within reach of verilator
 (#453)

* Move blackbox verilog implementations within reach of verilator
Blackbox implementers can annotate the modules with information on where to get the source verilog
This API is very lightweight, real work is done in firrtl in companion PR
Added some verilog to BlackBoxTest.v resource for testing

* if a file named black_box_verilog_files.f exists add a
-f black_box_verilog_files.f to the verilog to cpp command
---
 src/main/scala/chisel3/Driver.scala             | 19 ++++++++++++++++---
 src/main/scala/chisel3/util/BlackBoxUtils.scala | 24 ++++++++++++++++++++++++
 2 files changed, 40 insertions(+), 3 deletions(-)
 create mode 100644 src/main/scala/chisel3/util/BlackBoxUtils.scala

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index f4a7d0e5..f9f6dabe 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -113,10 +113,23 @@ trait BackendCompilationUtilities {
       vSources: Seq[File],
       cppHarness: File
                   ): ProcessBuilder = {
-    val command = Seq("verilator",
-      "--cc", s"$dutFile.v") ++
+    val blackBoxVerilogList = {
+      val list_file = new File(dir, firrtl.transforms.BlackBoxSourceHelper.FileListName)
+      if(list_file.exists()) {
+        Seq("-f", list_file.getAbsolutePath)
+      }
+      else {
+        Seq.empty[String]
+      }
+    }
+    val command = Seq(
+        "verilator",
+        "--cc", s"$dutFile.v"
+      ) ++
+      blackBoxVerilogList ++
       vSources.map(file => Seq("-v", file.toString)).flatten ++
-      Seq("--assert",
+      Seq(
+        "--assert",
         "-Wno-fatal",
         "-Wno-WIDTH",
         "-Wno-STMTDLY",
diff --git a/src/main/scala/chisel3/util/BlackBoxUtils.scala b/src/main/scala/chisel3/util/BlackBoxUtils.scala
new file mode 100644
index 00000000..084d58f9
--- /dev/null
+++ b/src/main/scala/chisel3/util/BlackBoxUtils.scala
@@ -0,0 +1,24 @@
+// See LICENSE for license details.
+
+package chisel3.util
+
+import chisel3._
+import chisel3.core.ChiselAnnotation
+import firrtl.transforms.{BlackBoxInline, BlackBoxResource, BlackBoxSourceHelper}
+
+trait HasBlackBoxResource extends BlackBox {
+  self: Module =>
+
+  def setResource(blackBoxResource: String): Unit = {
+    annotate(ChiselAnnotation(self, classOf[BlackBoxSourceHelper], BlackBoxResource(blackBoxResource).serialize))
+  }
+}
+
+trait HasBlackBoxInline extends BlackBox {
+  self: Module =>
+
+  def setInline(blackBoxName: String, blackBoxInline: String): Unit = {
+    annotate(ChiselAnnotation(
+      self, classOf[BlackBoxSourceHelper], BlackBoxInline(blackBoxName, blackBoxInline).serialize))
+  }
+}
-- 
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