From 556ce39b2b33787407a3634f775b6a2a9da086c8 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 8 Feb 2022 17:11:01 +0000 Subject: Overload getVerilogString to accept arguments (#2401) (#2402) (cherry picked from commit b55dc36d4edd1d22db37616235c003c89d68d29b) Co-authored-by: Carlos Eduardo --- src/main/scala/chisel3/verilog.scala | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'src/main') diff --git a/src/main/scala/chisel3/verilog.scala b/src/main/scala/chisel3/verilog.scala index b926a15c..c301ff98 100644 --- a/src/main/scala/chisel3/verilog.scala +++ b/src/main/scala/chisel3/verilog.scala @@ -4,7 +4,29 @@ import chisel3.stage.ChiselStage import firrtl.AnnotationSeq object getVerilogString { + + /** + * Returns a string containing the Verilog for the module specified by + * the target. + * + * @param gen the module to be converted to Verilog + * @return a string containing the Verilog for the module specified by + * the target + */ def apply(gen: => RawModule): String = ChiselStage.emitVerilog(gen) + + /** + * Returns a string containing the Verilog for the module specified by + * the target accepting arguments and annotations + * + * @param gen the module to be converted to Verilog + * @param args arguments to be passed to the compiler + * @param annotations annotations to be passed to the compiler + * @return a string containing the Verilog for the module specified by + * the target + */ + def apply(gen: => RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String = + (new ChiselStage).emitVerilog(gen, args, annotations) } object emitVerilog { -- cgit v1.2.3