From 4c48d5a94f9242f471e4c1ad39c664c672eafe13 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 30 Jan 2019 12:06:00 -0500 Subject: Add chisel3.stage.phases.Elaborate Phase This adds an Elaborate Phase that expands ChiselGeneratorAnnotations into ChiselCircuitAnnotations and deletes the original. Co-Authored-By: Schuyler Eldridge Co-Authored-By: chick Signed-off-by: Schuyler Eldridge --- .../scala/chisel3/stage/phases/Elaborate.scala | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 src/main/scala/chisel3/stage/phases/Elaborate.scala (limited to 'src/main') diff --git a/src/main/scala/chisel3/stage/phases/Elaborate.scala b/src/main/scala/chisel3/stage/phases/Elaborate.scala new file mode 100644 index 00000000..0b0d71fb --- /dev/null +++ b/src/main/scala/chisel3/stage/phases/Elaborate.scala @@ -0,0 +1,42 @@ +// See LICENSE for license details. + +package chisel3.stage.phases + +import java.io.{PrintWriter, StringWriter} + +import chisel3.ChiselException +import chisel3.internal.ErrorLog +import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOptions} +import firrtl.AnnotationSeq +import firrtl.options.Viewer.view +import firrtl.options.{OptionsException, Phase} + +/** Elaborate all [[chisel3.stage.ChiselGeneratorAnnotation]]s into [[chisel3.stage.ChiselCircuitAnnotation]]s. + */ +class Elaborate extends Phase { + + /** + * @todo Change this to print to STDERR (`Console.err.println`) + */ + def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap { + case a: ChiselGeneratorAnnotation => + try { + Some(a.elaborate) + } catch { + case e: OptionsException => throw e + case e: ChiselException => + val copts = view[ChiselOptions](annotations) + val stackTrace = if (!copts.printFullStackTrace) { + e.chiselStackTrace + } else { + val s = new StringWriter + e.printStackTrace(new PrintWriter(s)) + s.toString + } + Predef.augmentString(stackTrace).lines.foreach(line => println(s"${ErrorLog.errTag} $line")) + Some(a) + } + case a => Some(a) + } + +} -- cgit v1.2.3