From 6b658d740d976c7706c53c756acd069262d9ef59 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 2 Aug 2022 00:31:11 +0000 Subject: Remove remaining chiselNames (#2635) (#2656) (cherry picked from commit 8538269a14e0d5a1163298a79aa43b77a380aabc) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>--- src/main/scala/chisel3/compatibility.scala | 2 -- src/main/scala/chisel3/util/Decoupled.scala | 3 --- 2 files changed, 5 deletions(-) (limited to 'src/main') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index f3754e00..d140725f 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -4,7 +4,6 @@ * while moving to the more standard package naming convention `chisel3` (lowercase c). */ import chisel3._ // required for implicit conversions. -import chisel3.experimental.chiselName import chisel3.util.random.FibonacciLFSR import chisel3.stage.{phases, ChiselCircuitAnnotation, ChiselOutputFileAnnotation, ChiselStage} @@ -617,7 +616,6 @@ package object Chisel { /** Generates a 16-bit linear feedback shift register, returning the register contents. * @param increment optional control to gate when the LFSR updates. */ - @chiselName def apply(increment: Bool = true.B): UInt = VecInit( FibonacciLFSR diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index b21bd04f..f8c8f9e9 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -7,7 +7,6 @@ package chisel3.util import chisel3._ import chisel3.experimental.{requireIsChiselType, DataMirror, Direction} -import chisel3.internal.naming._ // can't use chisel3_ version because of compile order import scala.annotation.nowarn @@ -136,7 +135,6 @@ object Decoupled { * * @note unsafe (and will error) on the producer (input) side of an IrrevocableIO */ - @chiselName def apply[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = { require( DataMirror.directionOf(irr.bits) == Direction.Output, @@ -403,7 +401,6 @@ object Queue { * consumer.io.in <> Queue(producer.io.out, 16) * }}} */ - @chiselName def irrevocable[T <: Data]( enq: ReadyValidIO[T], entries: Int = 2, -- cgit v1.2.3 From c4dec947d54a52c3092bd7855180d42afaae3776 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Sat, 13 Aug 2022 00:17:56 +0000 Subject: Add option to treat warnings as errors (backport #2676) (#2677) * Add option to treat warnings as errors (#2676) Add --warnings-as-errors option (cherry picked from commit 498946663726955c380a1e420f5d7b9630000aad) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala # core/src/main/scala/chisel3/internal/Builder.scala # src/main/scala/chisel3/aop/injecting/InjectingAspect.scala # src/main/scala/chisel3/stage/ChiselOptions.scala # src/main/scala/chisel3/stage/package.scala # src/main/scala/chisel3/stage/phases/Elaborate.scala * Resolve backport conflicts Co-authored-by: Zachary Yedidia Co-authored-by: Jack Koenig --- .../scala/chisel3/aop/injecting/InjectingAspect.scala | 7 ++++++- src/main/scala/chisel3/stage/ChiselAnnotations.scala | 18 ++++++++++++++++++ src/main/scala/chisel3/stage/ChiselCli.scala | 1 + src/main/scala/chisel3/stage/ChiselOptions.scala | 3 +++ src/main/scala/chisel3/stage/package.scala | 1 + src/main/scala/chisel3/stage/phases/Elaborate.scala | 7 ++++++- 6 files changed, 35 insertions(+), 2 deletions(-) (limited to 'src/main') diff --git a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala index 087bdae2..ecce19e1 100644 --- a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala +++ b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala @@ -59,7 +59,12 @@ abstract class InjectorAspect[T <: RawModule, M <: RawModule]( RunFirrtlTransformAnnotation(new InjectingTransform) +: modules.map { module => val chiselOptions = view[ChiselOptions](annotationsInAspect) val dynamicContext = - new DynamicContext(annotationsInAspect, chiselOptions.throwOnFirstError, chiselOptions.warnReflectiveNaming) + new DynamicContext( + annotationsInAspect, + chiselOptions.throwOnFirstError, + chiselOptions.warnReflectiveNaming, + chiselOptions.warningsAsErrors + ) // Add existing module names into the namespace. If injection logic instantiates new modules // which would share the same name, they will get uniquified accordingly moduleNames.foreach { n => diff --git a/src/main/scala/chisel3/stage/ChiselAnnotations.scala b/src/main/scala/chisel3/stage/ChiselAnnotations.scala index eda05a7d..f65fabdc 100644 --- a/src/main/scala/chisel3/stage/ChiselAnnotations.scala +++ b/src/main/scala/chisel3/stage/ChiselAnnotations.scala @@ -79,6 +79,24 @@ case object ThrowOnFirstErrorAnnotation } +/** When enabled, warnings will be treated as errors. + */ +case object WarningsAsErrorsAnnotation + extends NoTargetAnnotation + with ChiselOption + with HasShellOptions + with Unserializable { + + val options = Seq( + new ShellOption[Unit]( + longOption = "warnings-as-errors", + toAnnotationSeq = _ => Seq(WarningsAsErrorsAnnotation), + helpText = "Treat warnings as errors" + ) + ) + +} + /** Warn when reflective naming changes names of signals */ case object WarnReflectiveNamingAnnotation extends NoTargetAnnotation diff --git a/src/main/scala/chisel3/stage/ChiselCli.scala b/src/main/scala/chisel3/stage/ChiselCli.scala index 8c5eb79a..60e30152 100644 --- a/src/main/scala/chisel3/stage/ChiselCli.scala +++ b/src/main/scala/chisel3/stage/ChiselCli.scala @@ -10,6 +10,7 @@ trait ChiselCli { this: Shell => NoRunFirrtlCompilerAnnotation, PrintFullStackTraceAnnotation, ThrowOnFirstErrorAnnotation, + WarningsAsErrorsAnnotation, WarnReflectiveNamingAnnotation, ChiselOutputFileAnnotation, ChiselGeneratorAnnotation diff --git a/src/main/scala/chisel3/stage/ChiselOptions.scala b/src/main/scala/chisel3/stage/ChiselOptions.scala index a03f3d7b..42a0ce68 100644 --- a/src/main/scala/chisel3/stage/ChiselOptions.scala +++ b/src/main/scala/chisel3/stage/ChiselOptions.scala @@ -9,6 +9,7 @@ class ChiselOptions private[stage] ( val printFullStackTrace: Boolean = false, val throwOnFirstError: Boolean = false, val warnReflectiveNaming: Boolean = false, + val warningsAsErrors: Boolean = false, val outputFile: Option[String] = None, val chiselCircuit: Option[Circuit] = None) { @@ -17,6 +18,7 @@ class ChiselOptions private[stage] ( printFullStackTrace: Boolean = printFullStackTrace, throwOnFirstError: Boolean = throwOnFirstError, warnReflectiveNaming: Boolean = warnReflectiveNaming, + warningsAsErrors: Boolean = warningsAsErrors, outputFile: Option[String] = outputFile, chiselCircuit: Option[Circuit] = chiselCircuit ): ChiselOptions = { @@ -26,6 +28,7 @@ class ChiselOptions private[stage] ( printFullStackTrace = printFullStackTrace, throwOnFirstError = throwOnFirstError, warnReflectiveNaming = warnReflectiveNaming, + warningsAsErrors = warningsAsErrors, outputFile = outputFile, chiselCircuit = chiselCircuit ) diff --git a/src/main/scala/chisel3/stage/package.scala b/src/main/scala/chisel3/stage/package.scala index 10c8c524..c76dac17 100644 --- a/src/main/scala/chisel3/stage/package.scala +++ b/src/main/scala/chisel3/stage/package.scala @@ -19,6 +19,7 @@ package object stage { case PrintFullStackTraceAnnotation => c.copy(printFullStackTrace = true) case ThrowOnFirstErrorAnnotation => c.copy(throwOnFirstError = true) case WarnReflectiveNamingAnnotation => c.copy(warnReflectiveNaming = true) + case WarningsAsErrorsAnnotation => c.copy(warningsAsErrors = true) case ChiselOutputFileAnnotation(f) => c.copy(outputFile = Some(f)) case ChiselCircuitAnnotation(a) => c.copy(chiselCircuit = Some(a)) } diff --git a/src/main/scala/chisel3/stage/phases/Elaborate.scala b/src/main/scala/chisel3/stage/phases/Elaborate.scala index ba29e5f2..a3fc4990 100644 --- a/src/main/scala/chisel3/stage/phases/Elaborate.scala +++ b/src/main/scala/chisel3/stage/phases/Elaborate.scala @@ -30,7 +30,12 @@ class Elaborate extends Phase { val chiselOptions = view[ChiselOptions](annotations) try { val context = - new DynamicContext(annotations, chiselOptions.throwOnFirstError, chiselOptions.warnReflectiveNaming) + new DynamicContext( + annotations, + chiselOptions.throwOnFirstError, + chiselOptions.warnReflectiveNaming, + chiselOptions.warningsAsErrors + ) val (circuit, dut) = Builder.build(Module(gen()), context) Seq(ChiselCircuitAnnotation(circuit), DesignAnnotation(dut)) -- cgit v1.2.3 From df5a95454ff0414d1d3ce16d06dbe27b152e3751 Mon Sep 17 00:00:00 2001 From: Zachary Yedidia Date: Thu, 25 Aug 2022 12:04:37 -0700 Subject: Backport of eager error messages for annotations (3.5.x) (#2700) (#2705) --- src/main/scala/chisel3/util/experimental/ForceNames.scala | 3 +++ src/main/scala/chisel3/util/experimental/decode/decoder.scala | 2 ++ 2 files changed, 5 insertions(+) (limited to 'src/main') diff --git a/src/main/scala/chisel3/util/experimental/ForceNames.scala b/src/main/scala/chisel3/util/experimental/ForceNames.scala index 53ee2bd2..3070a210 100644 --- a/src/main/scala/chisel3/util/experimental/ForceNames.scala +++ b/src/main/scala/chisel3/util/experimental/ForceNames.scala @@ -3,6 +3,7 @@ package chisel3.util.experimental import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform} +import chisel3.internal.Builder import firrtl.Mappers._ import firrtl._ import firrtl.annotations._ @@ -24,6 +25,7 @@ object forceName { * @param name Name to force to */ def apply[T <: chisel3.Element](signal: T, name: String): T = { + if (!signal.isSynthesizable) Builder.deprecated(s"Using forceName '$name' on non-hardware value $signal") annotate(new ChiselAnnotation with RunFirrtlTransform { def toFirrtl = ForceNameAnnotation(signal.toTarget, name) override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform] @@ -37,6 +39,7 @@ object forceName { * @param signal Signal to name */ def apply[T <: chisel3.Element](signal: T): T = { + if (!signal.isSynthesizable) Builder.deprecated(s"Using forceName on non-hardware value $signal") annotate(new ChiselAnnotation with RunFirrtlTransform { def toFirrtl = ForceNameAnnotation(signal.toTarget, signal.toTarget.ref) override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform] diff --git a/src/main/scala/chisel3/util/experimental/decode/decoder.scala b/src/main/scala/chisel3/util/experimental/decode/decoder.scala index 4feda672..067dd6f8 100644 --- a/src/main/scala/chisel3/util/experimental/decode/decoder.scala +++ b/src/main/scala/chisel3/util/experimental/decode/decoder.scala @@ -6,6 +6,7 @@ import chisel3._ import chisel3.experimental.{annotate, ChiselAnnotation} import chisel3.util.{pla, BitPat} import chisel3.util.experimental.{getAnnotations, BitSet} +import chisel3.internal.Builder import firrtl.annotations.Annotation import logger.LazyLogging @@ -30,6 +31,7 @@ object decoder extends LazyLogging { val (plaInput, plaOutput) = pla(minimizedTable.table.toSeq, BitPat(minimizedTable.default.value.U(minimizedTable.default.getWidth.W))) + assert(plaOutput.isSynthesizable, s"Using DecodeTableAnnotation on non-hardware value $plaOutput") annotate(new ChiselAnnotation { override def toFirrtl: Annotation = DecodeTableAnnotation(plaOutput.toTarget, truthTable.toString, minimizedTable.toString) -- cgit v1.2.3 From 45909f02e86edff010902c0317e813a8753837b9 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 20 Sep 2022 20:06:44 +0000 Subject: Use new lazy serialization in FIRRTL (#2741) (#2744) This enables emission of modules that serialize to >2 GiB of .fir text. (cherry picked from commit 2cbc852d09bb63cd5da291e5d5d942ab971952a4) Co-authored-by: Jack Koenig --- src/main/scala/chisel3/internal/firrtl/Emitter.scala | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'src/main') diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index bbf43a45..ca8562e8 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -11,12 +11,14 @@ private[chisel3] object Emitter { Serializer.serialize(fcircuit) } - def emitLazily(circuit: Circuit): Iterable[String] = { - val result = LazyList(s"circuit ${circuit.name} :\n") - val modules = circuit.components.view.map(Converter.convert) - val moduleStrings = modules.flatMap { m => - Array(Serializer.serialize(m, 1), "\n\n") + def emitLazily(circuit: Circuit): Iterable[String] = new Iterable[String] { + def iterator = { + val prelude = Iterator(s"circuit ${circuit.name} :\n") + val modules = circuit.components.iterator.map(Converter.convert) + val moduleStrings = modules.flatMap { m => + Serializer.lazily(m, 1) ++ Seq("\n\n") + } + prelude ++ moduleStrings } - result ++ moduleStrings } } -- cgit v1.2.3 From f2ef3a8ee378a307661bd598cd44d4b895b9352e Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 8 Nov 2022 07:05:53 +0000 Subject: Improve Record.bind and Detect Records with unstable elements (backport #2829) (#2831) * Add Aggregate.elementsIterator and micro-optimize elementsIterator provides a more efficient API for iterating on the elements of Aggregates. It is especially useful for Records where getElements returns a Seq and thus eagerly constructs a new datastructure which may then just be iterated on anyway. This new elementsIterator API is then used throughout the codebase where it makes sense. Also change Vec.getElements to just return the underlying self instead of constructing a new Seq. (cherry picked from commit defa440b349031475daeff4024fad04925cccee6) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala # core/src/main/scala/chisel3/Module.scala # core/src/main/scala/chisel3/experimental/Trace.scala * Move Aggregate.bind inline into Record.bind Vec overrides bind and does not call the version in Aggregate so the version in Aggregate is misleading in that its only ever used by Records. Now there is no version in Aggregate and the actual functionality and use is more clear. (cherry picked from commit b054c30ba47026cb2a9b28c696a0a0a58b1e2ee7) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala * Extract and optimize duplicate checking Record.bind This replaces an immutable.Map with a single mutable.HashSet and saves the allocation of # elements Seqs. (cherry picked from commit 832ea52bc23424bb75b9654422b725a9cafaef40) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala * Add check for Records that define def elements (cherry picked from commit a4f223415de19e2a732e0b6a8fe681f706a19a56) * Resolve backport conflicts * Make elementsIterator final and package private * Waive false MiMa failure Co-authored-by: Jack Koenig --- src/main/scala/chisel3/aop/Select.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/main') diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala index 3a2a8931..738d6f31 100644 --- a/src/main/scala/chisel3/aop/Select.scala +++ b/src/main/scala/chisel3/aop/Select.scala @@ -26,7 +26,7 @@ object Select { * @param d Component to find leafs if aggregate typed. Intermediate fields/indicies are not included */ def getLeafs(d: Data): Seq[Data] = d match { - case r: Record => r.getElements.flatMap(getLeafs) + case r: Record => r.elementsIterator.flatMap(getLeafs).toSeq case v: Vec[_] => v.getElements.flatMap(getLeafs) case other => Seq(other) } @@ -36,7 +36,7 @@ object Select { * @param d Component to find leafs if aggregate typed. Intermediate fields/indicies ARE included */ def getIntermediateAndLeafs(d: Data): Seq[Data] = d match { - case r: Record => r +: r.getElements.flatMap(getIntermediateAndLeafs) + case r: Record => r +: r.elementsIterator.flatMap(getIntermediateAndLeafs).toSeq case v: Vec[_] => v +: v.getElements.flatMap(getIntermediateAndLeafs) case other => Seq(other) } -- cgit v1.2.3