From 0e6eb5b35a442edf70ad37f963526609f2ba1f3c Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Mon, 14 Jan 2019 12:20:44 -0500 Subject: Add chisel.stage.phases.AddImplicitOutputFile Signed-off-by: Schuyler Eldridge --- .../stage/phases/AddImplicitOutputFile.scala | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala (limited to 'src/main') diff --git a/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala b/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala new file mode 100644 index 00000000..4a4dac72 --- /dev/null +++ b/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala @@ -0,0 +1,25 @@ +// See LICENSE for license details. + +package chisel3.stage.phases + +import firrtl.AnnotationSeq +import firrtl.options.Phase + +import chisel3.stage.{ChiselCircuitAnnotation, ChiselOutputFileAnnotation} + +/** Add a output file for a Chisel circuit, derived from the top module in the circuit, if no + * [[ChiselOutputFileAnnotation]] already exists. + */ +class AddImplicitOutputFile extends Phase { + + def transform(annotations: AnnotationSeq): AnnotationSeq = + annotations.collectFirst{ case _: ChiselOutputFileAnnotation => annotations }.getOrElse{ + + val x: Option[AnnotationSeq] = annotations + .collectFirst{ case a: ChiselCircuitAnnotation => + ChiselOutputFileAnnotation(a.circuit.name) +: annotations } + + x.getOrElse(annotations) + } + +} -- cgit v1.2.3