From 0d121a2e357511e9e7d975ae5f2d316e47cbf43b Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 25 May 2017 09:03:25 -0700
Subject: Update internal Pipe wiring - fixes #615" (#616)

Replace ambiguous bi-connect ("<>") with mono-connect (":=") for internal Pipe wiring.---
 src/main/scala/chisel3/util/Valid.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index f95bb17c..6fb67585 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -38,8 +38,8 @@ object Pipe
   def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T] = {
     if (latency == 0) {
       val out = Wire(Valid(enqBits))
-      out.valid <> enqValid
-      out.bits <> enqBits
+      out.valid := enqValid
+      out.bits := enqBits
       out
     } else {
       val v = RegNext(enqValid, false.B)
-- 
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