From 3120eefc8a73b5ab3d8f909445a3e004b5e60cc6 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 19 Jul 2016 15:08:22 -0700
Subject: Incorporate connection logic. Compiles but fails tests.

---
 src/main/scala/chisel3/package.scala        | 45 +++++++++++++++--------------
 src/main/scala/chisel3/util/Decoupled.scala | 14 ++++-----
 2 files changed, 31 insertions(+), 28 deletions(-)

(limited to 'src/main/scala')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 35bbd1c4..71ec0e92 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -3,15 +3,21 @@ package object chisel3 {
 
   import internal.firrtl.Width
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
-  
-  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
-    def U: UInt = UInt(x, Width())
-    def S: SInt = SInt(x, Width())
 
   import util.BitPat
 
 
   type Direction = chisel3.core.Direction
+  object Input {
+    def apply[T<:Data](target: T): T = chisel3.core.Input(target)
+  }
+  object Output {
+    def apply[T<:Data](target: T): T = chisel3.core.Output(target)
+  }
+  object Flipped {
+    def apply[T<:Data](target: T): T = chisel3.core.Flipped(target)
+  }
+
   type Data = chisel3.core.Data
   val Wire = chisel3.core.Wire
   val Clock = chisel3.core.Clock
@@ -63,30 +69,24 @@ package object chisel3 {
   *
   * Also provides .asBool to scala.Boolean and .asUInt to String
   *
-  * Note that, for stylistic reasons, one hould avoid extracting immediately
+  * Note that, for stylistic reasons, one should avoid extracting immediately
   * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
   * confusion (the 1 is a bit length and the 0 is a bit extraction position).
   * Prefer storing the result and then extracting from it.
   */
-  implicit class addLiteraltoScalaInt(val target: Int) extends AnyVal {
-    def asUInt() = UInt.Lit(target)
-    def asSInt() = SInt.Lit(target)
-    def asUInt(width: Int) = UInt.Lit(target, width)
-    def asSInt(width: Int) = SInt.Lit(target, width)
-
-    // These were recently added to chisel2/3 but are not to be used internally
-    @deprecated("asUInt should be used over U", "gchisel")
-    def U() = UInt.Lit(target)
-    @deprecated("asSInt should be used over S", "gchisel")
-    def S() = SInt.Lit(target)
-    @deprecated("asUInt should be used over U", "gchisel")
-    def U(width: Int) = UInt.Lit(target, width)
-    @deprecated("asSInt should be used over S", "gchisel")
-    def S(width: Int) = SInt.Lit(target, width)
-  }
   implicit class fromIntToLiteral(val x: Int) extends AnyVal {
     def U: UInt = UInt(BigInt(x), Width())
     def S: SInt = SInt(BigInt(x), Width())
+
+    def asUInt() = UInt(x, Width())
+    def asSInt() = SInt(x, Width())
+    def asUInt(width: Int) = UInt(x, width)
+    def asSInt(width: Int) = SInt(x, width)
+  }
+  
+  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
+    def U: UInt = UInt(x, Width())
+    def S: SInt = SInt(x, Width())
   }
   implicit class fromStringToLiteral(val x: String) extends AnyVal {
     def U: UInt = UInt(x)
@@ -104,4 +104,7 @@ package object chisel3 {
     def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
     def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
   }
+
+  val INPUT = chisel3.core.Direction.Input
+  val OUTPUT = chisel3.core.Direction.Output
 }
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 73f58ed4..4a6b72e9 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -12,8 +12,8 @@ class DecoupledIO[+T <: Data](gen: T) extends Bundle
 {
   val ready = Input(Bool())
   val valid = Output(Bool())
-  val bits  = Output(gen.newType)
-  override protected def cloneType: this.type = DecoupledIO(gen).asInstanceOf[this.type]
+  val bits  = Output(gen.cloneType)
+  override def cloneType: this.type = DecoupledIO(gen).asInstanceOf[this.type]
 }
 
 object DecoupledIO {
@@ -30,7 +30,7 @@ object DecoupledIO {
       * @return    dat.
       */
     def enq(dat: T): T = {
-      target.valid := true.asBool
+      target.valid := Bool(true)
       target.bits := dat
       dat
     }
@@ -38,7 +38,7 @@ object DecoupledIO {
     /** Indicate no enqueue occurs.  Valid is set to false, and all bits are set to zero.
       */
     def noenq(): Unit = {
-      target.valid := false.asBool
+      target.valid := Bool(false)
       target.bits := target.bits.fromBits(0.asUInt)
     }
 
@@ -48,17 +48,17 @@ object DecoupledIO {
       * @return the data for this device,
       */
     def deq(): T = {
-      target.ready := true.asBool
+      target.ready := Bool(true)
       target.bits
     }
 
     /** Indicate no dequeue occurs. Ready is set to false
       */
     def nodeq(): Unit = {
-      target.ready := false.asBool
+      target.ready := Bool(false)
     }
   }
-  override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; }
+//  override def cloneType: this.type = { DeqIO(gen).asInstanceOf[this.type]; }
 }
 
 object EnqIO {
-- 
cgit v1.2.3