From 8baa2ab806be1aa85a7a1da7b348726da1bd1d19 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 11 May 2017 15:07:30 -0700
Subject: Scope resources - move them down into chisel3 directory - fixes #549
 (#610)

---
 src/main/scala/chisel3/testers/TesterDriver.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/chisel3')

diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index fd3ad9ba..fc71f2b0 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -28,7 +28,7 @@ object TesterDriver extends BackendCompilationUtilities {
 
     // Copy CPP harness and other Verilog sources from resources into files
     val cppHarness =  new File(path, "top.cpp")
-    copyResourceToFile("/top.cpp", cppHarness)
+    copyResourceToFile("/chisel3/top.cpp", cppHarness)
     val additionalVFiles = additionalVResources.map((name: String) => {
       val mangledResourceName = name.replace("/", "_")
       val out = new File(path, mangledResourceName)
-- 
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