From 62daa09c61886bfeddfbaf2463d3cc08dbd15b71 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Tue, 6 Aug 2019 13:47:44 -0700
Subject: Avoid when(reset) construct in LFSR

Muxes and resets are only isomorphic with synchronous reset.  Use a reset
instead of a conditional to make this async-reset-safe.
---
 src/main/scala/chisel3/util/random/LFSR.scala | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

(limited to 'src/main/scala/chisel3/util/random/LFSR.scala')

diff --git a/src/main/scala/chisel3/util/random/LFSR.scala b/src/main/scala/chisel3/util/random/LFSR.scala
index a19f40d3..5b67c509 100644
--- a/src/main/scala/chisel3/util/random/LFSR.scala
+++ b/src/main/scala/chisel3/util/random/LFSR.scala
@@ -47,19 +47,24 @@ trait LFSR extends PRNG {
     */
   def reduction: LFSRReduce
 
-  seed match {
-    case Some(s) =>
-      reduction match {
+  override protected def resetValue: Vec[Bool] = seed match {
+    case Some(s) => reduction match {
         case XOR  => require(s != 0, "Seed cannot be zero")
         case XNOR => require(s != BigInt(2).pow(width) - 1, "Seed cannot be all ones (max value)")
       }
-    case None =>
+      super.resetValue
+
+    case None => {
+      val res = WireDefault(Vec(width, Bool()), DontCare)
+
       reduction match {
-        case XOR  => when (reset.toBool) { state(0) := 1.U }
-        case XNOR => when (reset.toBool) { state(0) := 0.U }
+        case XOR  => res(0) := true.B
+        case XNOR => res(0) := false.B
       }
-  }
 
+      res
+    }
+  }
 }
 
 /** Utilities related to psuedorandom number generation using Linear Feedback Shift Registers (LFSRs).
-- 
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