From 356d5c99c233540e4d993ccc365a7069d9d2beaa Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Thu, 9 May 2019 16:48:36 -0400 Subject: PRNG state UInt->Vec[Bool], make async reset safe Changes the internal state of PRNG to use Vec[Bool] instead of UInt. This fixes an @aswaterman identified future problem with asynchronous reset. A register with an asynchronous reset can only be reset to a literal. Previously, an LFSR would store state as a UInt. If it was not parameterized with a seed it should have its least significant bit reset to something to avoid locking up. It's ideal to not reset the full UInt (better test coverage, decreased reset fanout). However, it's difficult to only reset one bit of a UInt. Conversely, it's trivial to reset one bit of a Vec[Bool]. This also moves PRNG/LFSR closer to a canonical representation of their internal state, i.e., it's natural to think of generalizing Vec[Bool] to arbitrary finite fields (Vec[A <: Field]) whereas UInt is tightly coupled to GF2. Minor updates: - Updates/fixes to some scaladoc - Add assertion to period test to make sure LFSR is changing Signed-off-by: Schuyler Eldridge --- src/main/scala/chisel3/util/random/LFSR.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/main/scala/chisel3/util/random/LFSR.scala') diff --git a/src/main/scala/chisel3/util/random/LFSR.scala b/src/main/scala/chisel3/util/random/LFSR.scala index 6663940c..a19f40d3 100644 --- a/src/main/scala/chisel3/util/random/LFSR.scala +++ b/src/main/scala/chisel3/util/random/LFSR.scala @@ -55,8 +55,8 @@ trait LFSR extends PRNG { } case None => reduction match { - case XOR => when (reset.toBool) { state := state(width-1, 1) ## 1.U } - case XNOR => when (reset.toBool) { state := state(width-1, 1) ## 0.U } + case XOR => when (reset.toBool) { state(0) := 1.U } + case XNOR => when (reset.toBool) { state(0) := 0.U } } } -- cgit v1.2.3