From 315923aa09101f6c6ffc58a445bd7411b3b23fca Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Tue, 6 Aug 2024 07:51:25 -0700
Subject: Fix more misc files

---
 src/main/scala/chisel3/util/experimental/BoringUtils.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/chisel3/util/experimental')

diff --git a/src/main/scala/chisel3/util/experimental/BoringUtils.scala b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
index 254f83a4..0bbe000d 100644
--- a/src/main/scala/chisel3/util/experimental/BoringUtils.scala
+++ b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
@@ -4,7 +4,7 @@ package chisel3.util.experimental
 
 import chisel3._
 import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform}
-import chisel3.internal.{InstanceId, NamedComponent, Namespace}
+import chisel3.internal.{NamedComponent, Namespace}
 import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
 import firrtl.passes.wiring.{SinkAnnotation, SourceAnnotation, WiringTransform}
 import firrtl.annotations.{ComponentName, ModuleName}
-- 
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