From a79f57565e7157d137628d1aaeae750f98e3d88b Mon Sep 17 00:00:00 2001 From: Abongwa Bonalais Date: Wed, 3 Nov 2021 05:56:37 +0100 Subject: Add field grouping ScalaDoc for other subclasses of Bundle (#2214) * Add field grouping scaladocs for DecoupledIo * Added groupdesc to DecoupledIO * Added groupings for IrrevocableIO * Add groupings for ValidIO * Add field grouping scaladoc for PRNGIO * Add field grouping scaladoc for QueueIO * Added groupings for PipeIO * Update src/main/scala/chisel3/util/Decoupled.scala Commited Sugestion Co-authored-by: Megan Wachs * Update src/main/scala/chisel3/util/Decoupled.scala Co-authored-by: Megan Wachs * Update src/main/scala/chisel3/util/Decoupled.scala Co-authored-by: Megan Wachs * Update src/main/scala/chisel3/util/Decoupled.scala Co-authored-by: Megan Wachs * Update src/main/scala/chisel3/util/Decoupled.scala Co-authored-by: Megan Wachs * Update src/main/scala/chisel3/util/Valid.scala Co-authored-by: Megan Wachs * Update src/main/scala/chisel3/util/Valid.scala Co-authored-by: Megan Wachs * Update src/main/scala/chisel3/util/Valid.scala Co-authored-by: Megan Wachs Co-authored-by: Megan Wachs --- src/main/scala/chisel3/util/Valid.scala | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'src/main/scala/chisel3/util/Valid.scala') diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index 4d348014..5d80502a 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -17,12 +17,17 @@ import chisel3._ * @tparam T the type of the data * @param gen some data * @see [[Valid$ Valid factory]] for concrete examples + * @groupdesc Signals The actual hardware fields of the Bundle */ class Valid[+T <: Data](gen: T) extends Bundle { - /** A bit that will be asserted when `bits` is valid */ + /** A bit that will be asserted when `bits` is valid + * @group Signals + */ val valid = Output(Bool()) - /** Some data */ + /** The data to be transferred, qualified by `valid` + * @group Signals + */ val bits = Output(gen) /** True when `valid` is asserted @@ -173,13 +178,18 @@ class Pipe[T <: Data](val gen: T, val latency: Int = 1)(implicit compileOptions: /** Interface for [[Pipe]]s composed of a [[Valid]] input and [[Valid]] output * @define notAQueue + * @groupdesc Signals Hardware fields of the Bundle */ class PipeIO extends Bundle { - /** [[Valid]] input */ + /** [[Valid]] input + * @group Signals + */ val enq = Input(Valid(gen)) - /** [[Valid]] output. Data will appear here `latency` cycles after being valid at `enq`. */ + /** [[Valid]] output. Data will appear here `latency` cycles after being valid at `enq`. + * @group Signals + */ val deq = Output(Valid(gen)) } -- cgit v1.2.3