From 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:01:03 -0800
Subject: Restyle a lot of test code, mainly with regex

---
 src/main/scala/chisel3/util/Valid.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/chisel3/util/Valid.scala')

diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 3d153a2a..49a6f515 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -41,7 +41,7 @@ object Pipe
       out.bits <> enqBits
       out
     } else {
-      val v = Reg(Bool(), next=enqValid, init=Bool(false))
+      val v = Reg(Bool(), next=enqValid, init=false.B)
       val b = RegEnable(enqBits, enqValid)
       apply(v, b, latency-1)
     }
-- 
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