From 36506c527ff0f51636beee4160f0ce1f6ad2f90a Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Wed, 15 Dec 2021 15:53:52 +0800
Subject: Refactor TruthTable to use Seq (#2217)

This makes the resulting Verilog from decoding a TruthTable deterministic.---
 src/main/scala/chisel3/util/BitPat.scala | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/main/scala/chisel3/util/BitPat.scala')

diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 4b94879f..4f8ae504 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -8,6 +8,12 @@ import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
 
 object BitPat {
+
+  private[chisel3] implicit val bitPatOrder = new Ordering[BitPat] {
+    import scala.math.Ordered.orderingToOrdered
+    def compare(x: BitPat, y: BitPat): Int = (x.getWidth, x.value, x.mask) compare (y.getWidth, y.value, y.mask)
+  }
+
   /** Parses a bit pattern string into (bits, mask, width).
     *
     * @return bits the literal value, with don't cares being 0
-- 
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