From c5f9ea3133ef363ff8944e17d94fea79767b6bed Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 6 Jul 2016 10:01:23 -0700 Subject: Rename "Chisel" to "chisel3" (only git mv). --- src/main/scala/chisel3/util/Arbiter.scala | 117 ++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 src/main/scala/chisel3/util/Arbiter.scala (limited to 'src/main/scala/chisel3/util/Arbiter.scala') diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala new file mode 100644 index 00000000..16ae9be5 --- /dev/null +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -0,0 +1,117 @@ +// See LICENSE for license details. + +/** Arbiters in all shapes and sizes. + */ + +package Chisel + +/** An I/O bundle for the Arbiter */ +class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { + val in = Vec(n, Decoupled(gen)).flip + val out = Decoupled(gen) + val chosen = UInt(OUTPUT, log2Up(n)) +} + +/** Arbiter Control determining which producer has access */ +private object ArbiterCtrl +{ + def apply(request: Seq[Bool]): Seq[Bool] = request.length match { + case 0 => Seq() + case 1 => Seq(Bool(true)) + case _ => Bool(true) +: request.tail.init.scanLeft(request.head)(_ || _).map(!_) + } +} + +abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module { + def grant: Seq[Bool] + def choice: UInt + val io = new ArbiterIO(gen, n) + + io.chosen := choice + io.out.valid := io.in(io.chosen).valid + io.out.bits := io.in(io.chosen).bits + + if (count > 1) { + val lockCount = Counter(count) + val lockIdx = Reg(UInt()) + val locked = lockCount.value =/= UInt(0) + val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true)) + + when (io.out.fire() && wantsLock) { + lockIdx := io.chosen + lockCount.inc() + } + + when (locked) { io.chosen := lockIdx } + for ((in, (g, i)) <- io.in zip grant.zipWithIndex) + in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready + } else { + for ((in, g) <- io.in zip grant) + in.ready := g && io.out.ready + } +} + +class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) + extends LockingArbiterLike[T](gen, n, count, needsLock) { + lazy val lastGrant = RegEnable(io.chosen, io.out.fire()) + lazy val grantMask = (0 until n).map(UInt(_) > lastGrant) + lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g } + + override def grant: Seq[Bool] = { + val ctrl = ArbiterCtrl((0 until n).map(i => validMask(i)) ++ io.in.map(_.valid)) + (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n)) + } + + override lazy val choice = Wire(init=UInt(n-1)) + for (i <- n-2 to 0 by -1) + when (io.in(i).valid) { choice := UInt(i) } + for (i <- n-1 to 1 by -1) + when (validMask(i)) { choice := UInt(i) } +} + +class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) + extends LockingArbiterLike[T](gen, n, count, needsLock) { + def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid)) + + override lazy val choice = Wire(init=UInt(n-1)) + for (i <- n-2 to 0 by -1) + when (io.in(i).valid) { choice := UInt(i) } +} + +/** Hardware module that is used to sequence n producers into 1 consumer. + Producers are chosen in round robin order. + + Example usage: + val arb = new RRArbiter(2, UInt()) + arb.io.in(0) <> producer0.io.out + arb.io.in(1) <> producer1.io.out + consumer.io.in <> arb.io.out + */ +class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1) + +/** Hardware module that is used to sequence n producers into 1 consumer. + Priority is given to lower producer + + Example usage: + val arb = Module(new Arbiter(2, UInt())) + arb.io.in(0) <> producer0.io.out + arb.io.in(1) <> producer1.io.out + consumer.io.in <> arb.io.out + */ +class Arbiter[T <: Data](gen: T, n: Int) extends Module { + val io = new ArbiterIO(gen, n) + + io.chosen := UInt(n-1) + io.out.bits := io.in(n-1).bits + for (i <- n-2 to 0 by -1) { + when (io.in(i).valid) { + io.chosen := UInt(i) + io.out.bits := io.in(i).bits + } + } + + val grant = ArbiterCtrl(io.in.map(_.valid)) + for ((in, g) <- io.in zip grant) + in.ready := g && io.out.ready + io.out.valid := !grant.last || io.in.last.valid +} -- cgit v1.2.3 From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 6 Jul 2016 09:31:47 -0700 Subject: Update Chisel -> chisel3 references. --- src/main/scala/chisel3/util/Arbiter.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/main/scala/chisel3/util/Arbiter.scala') diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 16ae9be5..eb541977 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -3,7 +3,9 @@ /** Arbiters in all shapes and sizes. */ -package Chisel +package chisel3.util + +import chisel3._ /** An I/O bundle for the Arbiter */ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { -- cgit v1.2.3 From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 14:49:35 -0700 Subject: Distinguish between ?Int.Lit and ?Int.width --- src/main/scala/chisel3/util/Arbiter.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/main/scala/chisel3/util/Arbiter.scala') diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index a5397682..44cc88b6 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -36,7 +36,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo if (count > 1) { val lockCount = Counter(count) val lockIdx = Reg(UInt()) - val locked = lockCount.value =/= UInt(0) + val locked = lockCount.value =/= UInt.Lit(0) val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true)) when (io.out.firing && wantsLock) { @@ -46,7 +46,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo when (locked) { io.chosen := lockIdx } for ((in, (g, i)) <- io.in zip grant.zipWithIndex) - in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready + in.ready := Mux(locked, lockIdx === UInt.Lit(i), g) && io.out.ready } else { for ((in, g) <- io.in zip grant) in.ready := g && io.out.ready @@ -66,9 +66,9 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[ override lazy val choice = Wire(init=UInt(n-1)) for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt(i) } + when (io.in(i).valid) { choice := UInt.Lit(i) } for (i <- n-1 to 1 by -1) - when (validMask(i)) { choice := UInt(i) } + when (validMask(i)) { choice := UInt.Lit(i) } } class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) @@ -77,7 +77,7 @@ class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T override lazy val choice = Wire(init=UInt(n-1)) for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt(i) } + when (io.in(i).valid) { choice := UInt.Lit(i) } } /** Hardware module that is used to sequence n producers into 1 consumer. @@ -107,7 +107,7 @@ class Arbiter[T <: Data](gen: T, n: Int) extends Module { io.out.bits := io.in(n-1).bits for (i <- n-2 to 0 by -1) { when (io.in(i).valid) { - io.chosen := UInt(i) + io.chosen := UInt.Lit(i) io.out.bits := io.in(i).bits } } -- cgit v1.2.3 From 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 17:08:55 -0700 Subject: More literal/width rangling. --- src/main/scala/chisel3/util/Arbiter.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/main/scala/chisel3/util/Arbiter.scala') diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 44cc88b6..0ece3a0a 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -11,7 +11,7 @@ import chisel3._ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { val in = Flipped(Vec(n, DecoupledIO(gen))) val out = DecoupledIO(gen) - val chosen = Output(UInt(log2Up(n))) + val chosen = Output(UInt.width(log2Up(n))) } /** Arbiter Control determining which producer has access */ @@ -56,7 +56,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) extends LockingArbiterLike[T](gen, n, count, needsLock) { lazy val lastGrant = RegEnable(io.chosen, io.out.firing) - lazy val grantMask = (0 until n).map(UInt(_) > lastGrant) + lazy val grantMask = (0 until n).map(UInt.Lit(_) > lastGrant) lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g } override def grant: Seq[Bool] = { @@ -64,7 +64,7 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[ (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n)) } - override lazy val choice = Wire(init=UInt(n-1)) + override lazy val choice = Wire(init=UInt.Lit(n-1)) for (i <- n-2 to 0 by -1) when (io.in(i).valid) { choice := UInt.Lit(i) } for (i <- n-1 to 1 by -1) @@ -75,7 +75,7 @@ class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T extends LockingArbiterLike[T](gen, n, count, needsLock) { def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid)) - override lazy val choice = Wire(init=UInt(n-1)) + override lazy val choice = Wire(init=UInt.Lit(n-1)) for (i <- n-2 to 0 by -1) when (io.in(i).valid) { choice := UInt.Lit(i) } } @@ -103,7 +103,7 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1) class Arbiter[T <: Data](gen: T, n: Int) extends Module { val io = IO(new ArbiterIO(gen, n)) - io.chosen := UInt(n-1) + io.chosen := UInt.Lit(n-1) io.out.bits := io.in(n-1).bits for (i <- n-2 to 0 by -1) { when (io.in(i).valid) { -- cgit v1.2.3 From 7aa05590382b0528799ad5e9f1318ce42e409793 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 25 Jul 2016 14:06:51 -0700 Subject: Minimize differences with master. Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. --- src/main/scala/chisel3/util/Arbiter.scala | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'src/main/scala/chisel3/util/Arbiter.scala') diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 0ece3a0a..5875b3f2 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -36,17 +36,17 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo if (count > 1) { val lockCount = Counter(count) val lockIdx = Reg(UInt()) - val locked = lockCount.value =/= UInt.Lit(0) + val locked = lockCount.value =/= UInt(0) val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true)) - when (io.out.firing && wantsLock) { + when (io.out.fire() && wantsLock) { lockIdx := io.chosen lockCount.inc() } when (locked) { io.chosen := lockIdx } for ((in, (g, i)) <- io.in zip grant.zipWithIndex) - in.ready := Mux(locked, lockIdx === UInt.Lit(i), g) && io.out.ready + in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready } else { for ((in, g) <- io.in zip grant) in.ready := g && io.out.ready @@ -55,8 +55,8 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) extends LockingArbiterLike[T](gen, n, count, needsLock) { - lazy val lastGrant = RegEnable(io.chosen, io.out.firing) - lazy val grantMask = (0 until n).map(UInt.Lit(_) > lastGrant) + lazy val lastGrant = RegEnable(io.chosen, io.out.fire()) + lazy val grantMask = (0 until n).map(UInt(_) > lastGrant) lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g } override def grant: Seq[Bool] = { @@ -64,20 +64,20 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[ (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n)) } - override lazy val choice = Wire(init=UInt.Lit(n-1)) + override lazy val choice = Wire(init=UInt(n-1)) for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt.Lit(i) } + when (io.in(i).valid) { choice := UInt(i) } for (i <- n-1 to 1 by -1) - when (validMask(i)) { choice := UInt.Lit(i) } + when (validMask(i)) { choice := UInt(i) } } class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) extends LockingArbiterLike[T](gen, n, count, needsLock) { def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid)) - override lazy val choice = Wire(init=UInt.Lit(n-1)) + override lazy val choice = Wire(init=UInt(n-1)) for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt.Lit(i) } + when (io.in(i).valid) { choice := UInt(i) } } /** Hardware module that is used to sequence n producers into 1 consumer. @@ -103,11 +103,11 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1) class Arbiter[T <: Data](gen: T, n: Int) extends Module { val io = IO(new ArbiterIO(gen, n)) - io.chosen := UInt.Lit(n-1) + io.chosen := UInt(n-1) io.out.bits := io.in(n-1).bits for (i <- n-2 to 0 by -1) { when (io.in(i).valid) { - io.chosen := UInt.Lit(i) + io.chosen := UInt(i) io.out.bits := io.in(i).bits } } -- cgit v1.2.3 From 6df3a785f8abe706838bc5b4b35c3374b6512f96 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 29 Aug 2016 12:17:48 -0700 Subject: Pass compileOptions as an implicit Module parameter. --- src/main/scala/chisel3/util/Arbiter.scala | 1 + 1 file changed, 1 insertion(+) (limited to 'src/main/scala/chisel3/util/Arbiter.scala') diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 5875b3f2..57e81708 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -6,6 +6,7 @@ package chisel3.util import chisel3._ +import chisel3.NotStrict.NotStrictCompileOptions /** An I/O bundle for the Arbiter */ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { -- cgit v1.2.3 From 62817134d222747f1eab34626fe7b1bb13b9f6df Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 29 Aug 2016 13:45:05 -0700 Subject: Rename CompileOptions implicit objects. --- src/main/scala/chisel3/util/Arbiter.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/main/scala/chisel3/util/Arbiter.scala') diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 57e81708..5d46b7b9 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -6,7 +6,7 @@ package chisel3.util import chisel3._ -import chisel3.NotStrict.NotStrictCompileOptions +import chisel3.NotStrict.CompileOptions /** An I/O bundle for the Arbiter */ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { -- cgit v1.2.3 From 6d8acee760c8c41fcae2ab252161bac96e6954dc Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Fri, 16 Sep 2016 09:07:15 -0700 Subject: Rename DecoupledIO object to Decoupled (compatibility). --- src/main/scala/chisel3/util/Arbiter.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/main/scala/chisel3/util/Arbiter.scala') diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 5d46b7b9..c80f1908 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -10,8 +10,8 @@ import chisel3.NotStrict.CompileOptions /** An I/O bundle for the Arbiter */ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { - val in = Flipped(Vec(n, DecoupledIO(gen))) - val out = DecoupledIO(gen) + val in = Flipped(Vec(n, Decoupled(gen))) + val out = Decoupled(gen) val chosen = Output(UInt.width(log2Up(n))) } -- cgit v1.2.3 From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 29 Sep 2016 11:44:09 -0700 Subject: Massive rename of CompileOptions. Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports. NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence). We should really thread the CompileOptions through the macro system so the client's implicits are used. --- src/main/scala/chisel3/util/Arbiter.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/main/scala/chisel3/util/Arbiter.scala') diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 67e28617..adeb1b34 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -6,7 +6,7 @@ package chisel3.util import chisel3._ -import chisel3.NotStrict.CompileOptions +//import chisel3.ExplicitCompileOptions.NotStrict /** IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs * (selects) at most one. -- cgit v1.2.3 From 96fb6a5e2c781b20470d02eac186b1b129c20bdf Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 29 Sep 2016 14:57:42 -0700 Subject: Consolidate CompileOptions and re-enable NotStrict pending macro work. --- src/main/scala/chisel3/util/Arbiter.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/main/scala/chisel3/util/Arbiter.scala') diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index adeb1b34..89bb644a 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -6,7 +6,8 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.NotStrict +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict /** IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs * (selects) at most one. -- cgit v1.2.3