From 9e992816e570284193e121cd9c24503fd8cb4427 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Mon, 21 Jan 2019 16:24:43 -0800
Subject: Unify internal (chisel3.core) and external (chisel3 /
 chisel3.experimental) Module class names (#994)

---
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/chisel3/internal')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index ac4bf8e7..68513423 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -110,7 +110,7 @@ private class Emitter(circuit: Circuit) {
     */
   private def moduleDecl(m: Component): String = m.id match {
     case _: chisel3.core.BaseBlackBox => newline + s"extmodule ${m.name} : "
-    case _: chisel3.core.UserModule => newline + s"module ${m.name} : "
+    case _: chisel3.core.RawModule => newline + s"module ${m.name} : "
   }
 
   /** Generates the FIRRTL module definition.
-- 
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