From 66a72ff64c46d8a9fdade77223de62b4dcfe2825 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 21 Dec 2016 14:33:07 -0800
Subject: Add Analog type

Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
---
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/main/scala/chisel3/internal')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 42bc6c30..eb00e333 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -25,6 +25,7 @@ private class Emitter(circuit: Circuit) {
       case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
       case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}"
       case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
+      case e: Attach => e.locs.map(_.fullName(ctx)).mkString("attach (", ", ", ")")
       case e: Stop => s"stop(${e.clock.fullName(ctx)}, UInt<1>(1), ${e.ret})"
       case e: Printf =>
         val (fmt, args) = e.pable.unpack(ctx)
-- 
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