From f45216effc573d33d4aa4e525cff955ab332efbd Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Thu, 4 Feb 2021 00:36:12 +0000
Subject: Remove Deprecated APIs (#1730)

---
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/chisel3/internal')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 354be0c0..ad4df80a 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -29,7 +29,7 @@ private class Emitter(circuit: Circuit) {
     case d: Clock => "Clock"
     case _: AsyncReset => "AsyncReset"
     case _: ResetType => "Reset"
-    case d: chisel3.core.EnumType => s"UInt${d.width}"
+    case d: chisel3.experimental.EnumType => s"UInt${d.width}"
     case d: UInt => s"UInt${d.width}"
     case d: SInt => s"SInt${d.width}"
     case d: FixedPoint => s"Fixed${d.width}${d.binaryPoint}"
-- 
cgit v1.2.3


From f8053db3d20b733e0119b77595f0cdfcdab71057 Mon Sep 17 00:00:00 2001
From: Deborah Soung
Date: Thu, 24 Jun 2021 14:03:28 -0700
Subject: create and extend annotatable BaseSim class for verification nodes
 (#1968)

* prototype annotating verif constructs

* switch to final class

* name emissions

* moving BaseSim to experimental

* adding name tests

* fixing quotation escapes

* emitting names, but everything has a default name

* only name things with provided/suggested names

* name every BaseSim node

* removing msg, unused imports

* fixing file exist calls---
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main/scala/chisel3/internal')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index ad4df80a..53d5c6ce 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -80,8 +80,8 @@ private class Emitter(circuit: Circuit) {
         val printfArgs = Seq(e.clock.fullName(ctx), "UInt<1>(1)",
           "\"" + printf.format(fmt) + "\"") ++ args
         printfArgs mkString ("printf(", ", ", ")")
-      case e: Verification => s"${e.op}(${e.clock.fullName(ctx)}, ${e.predicate.fullName(ctx)}, " +
-        s"UInt<1>(1), " + "\"" + s"${printf.format(e.message)}" + "\")"
+      case e: Verification[_] =>
+        s"""${e.op}(${e.clock.fullName(ctx)}, ${e.predicate.fullName(ctx)}, UInt<1>(1), "${printf.format(e.message)}") : ${e.name}"""
       case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"
       case e: DefInstance => s"inst ${e.name} of ${e.id.name}"
       case w: WhenBegin =>
-- 
cgit v1.2.3


From 503ae520e7f997bcbc639b79869c9a4214d402ed Mon Sep 17 00:00:00 2001
From: Deborah Soung
Date: Tue, 6 Jul 2021 14:40:59 -0700
Subject: Make printf return BaseSim subclass so it can be named/annotated
 (#1992)

---
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main/scala/chisel3/internal')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 53d5c6ce..47849d91 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -75,11 +75,11 @@ private class Emitter(circuit: Circuit) {
       case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
       case e: Attach => e.locs.map(_.fullName(ctx)).mkString("attach (", ", ", ")")
       case e: Stop => s"stop(${e.clock.fullName(ctx)}, UInt<1>(1), ${e.ret})"
-      case e: Printf =>
+      case e: chisel3.internal.firrtl.Printf =>
         val (fmt, args) = e.pable.unpack(ctx)
         val printfArgs = Seq(e.clock.fullName(ctx), "UInt<1>(1)",
           "\"" + printf.format(fmt) + "\"") ++ args
-        printfArgs mkString ("printf(", ", ", ")")
+        (printfArgs mkString ("printf(", ", ", ")")) + s": ${e.name}"
       case e: Verification[_] =>
         s"""${e.op}(${e.clock.fullName(ctx)}, ${e.predicate.fullName(ctx)}, UInt<1>(1), "${printf.format(e.message)}") : ${e.name}"""
       case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"
-- 
cgit v1.2.3


From ed894c61474c8bc73761a6c360ef9d14505d853b Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Wed, 18 Aug 2021 03:44:17 +0800
Subject: remove DefRegInit, change DefReg API with option definition. (#1944)

* remove DefRegInit, change DefReg API with option defination.

* add error message

* use Option[RegInitIR].

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src/main/scala/chisel3/internal')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 47849d91..daa83db0 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -66,8 +66,7 @@ private class Emitter(circuit: Circuit) {
     val firrtlLine = e match {
       case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})"
       case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}"
-      case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}"
-      case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"
+      case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}${ if (e.regInit.isDefined) "with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" else ""}"
       case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]"
       case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}"
       case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
-- 
cgit v1.2.3


From 7c8a032e7e23902283035d93579b8dc477b32f6a Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 17 Aug 2021 18:22:16 -0700
Subject: Revert "remove DefRegInit, change DefReg API with option definition.
 (#1944)" (#2080)

This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.---
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/main/scala/chisel3/internal')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index daa83db0..47849d91 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -66,7 +66,8 @@ private class Emitter(circuit: Circuit) {
     val firrtlLine = e match {
       case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})"
       case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}"
-      case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}${ if (e.regInit.isDefined) "with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" else ""}"
+      case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}"
+      case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"
       case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]"
       case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}"
       case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
-- 
cgit v1.2.3


From 73bd4ee6b9b510725b692c33e075362a19512d2c Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 20 Aug 2021 11:30:27 -0700
Subject: Remove chisel3's own firrtl Emitter, use firrtl Serializer

This will be slightly slower as it involves converting from Chisel
modules to FIRRTL modules before turning them into Strings. This cost is
somewhat mitigated by doing that conversion lazily such that we never
materialize the entire firrtl Circuit in memory, only 1 module at a
time.
---
 .../scala/chisel3/internal/firrtl/Emitter.scala    | 192 +--------------------
 1 file changed, 5 insertions(+), 187 deletions(-)

(limited to 'src/main/scala/chisel3/internal')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 47849d91..53329908 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -1,194 +1,12 @@
 // SPDX-License-Identifier: Apache-2.0
 
 package chisel3.internal.firrtl
-import chisel3._
-import chisel3.experimental.{Interval, _}
-import chisel3.internal.BaseBlackBox
+import firrtl.{ir => fir}
 
 private[chisel3] object Emitter {
-  def emit(circuit: Circuit): String = new Emitter(circuit).toString
-}
-
-private class Emitter(circuit: Circuit) {
-  override def toString: String = res.toString
-
-  private def emitPort(e: Port, topDir: SpecifiedDirection=SpecifiedDirection.Unspecified): String = {
-    val resolvedDir = SpecifiedDirection.fromParent(topDir, e.dir)
-    val dirString = resolvedDir match {
-      case SpecifiedDirection.Unspecified | SpecifiedDirection.Output => "output"
-      case SpecifiedDirection.Flip | SpecifiedDirection.Input => "input"
-    }
-    val clearDir = resolvedDir match {
-      case SpecifiedDirection.Input | SpecifiedDirection.Output => true
-      case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => false
-    }
-    s"$dirString ${e.id.getRef.name} : ${emitType(e.id, clearDir)}"
-  }
-
-  private def emitType(d: Data, clearDir: Boolean = false): String = d match {
-    case d: Clock => "Clock"
-    case _: AsyncReset => "AsyncReset"
-    case _: ResetType => "Reset"
-    case d: chisel3.experimental.EnumType => s"UInt${d.width}"
-    case d: UInt => s"UInt${d.width}"
-    case d: SInt => s"SInt${d.width}"
-    case d: FixedPoint => s"Fixed${d.width}${d.binaryPoint}"
-    case d: Interval =>
-      val binaryPointString = d.binaryPoint match {
-        case UnknownBinaryPoint => ""
-        case KnownBinaryPoint(value) => s".$value"
-      }
-      d.toType
-    case d: Analog => s"Analog${d.width}"
-    case d: Vec[_] => s"${emitType(d.sample_element, clearDir)}[${d.length}]"
-    case d: Record => {
-      val childClearDir = clearDir ||
-          d.specifiedDirection == SpecifiedDirection.Input || d.specifiedDirection == SpecifiedDirection.Output
-      def eltPort(elt: Data): String = (childClearDir, firrtlUserDirOf(elt)) match {
-        case (true, _) =>
-          s"${elt.getRef.name} : ${emitType(elt, true)}"
-        case (false, SpecifiedDirection.Unspecified | SpecifiedDirection.Output) =>
-          s"${elt.getRef.name} : ${emitType(elt, false)}"
-        case (false, SpecifiedDirection.Flip | SpecifiedDirection.Input) =>
-          s"flip ${elt.getRef.name} : ${emitType(elt, false)}"
-      }
-      d.elements.toIndexedSeq.reverse.map(e => eltPort(e._2)).mkString("{", ", ", "}")
-    }
-  }
-
-  private def firrtlUserDirOf(d: Data): SpecifiedDirection = d match {
-    case d: Vec[_] =>
-      SpecifiedDirection.fromParent(d.specifiedDirection, firrtlUserDirOf(d.sample_element))
-    case d => d.specifiedDirection
-  }
-
-  private def emit(e: Command, ctx: Component): String = {
-    val firrtlLine = e match {
-      case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})"
-      case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}"
-      case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}"
-      case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"
-      case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]"
-      case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}"
-      case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
-      case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}"
-      case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
-      case e: Attach => e.locs.map(_.fullName(ctx)).mkString("attach (", ", ", ")")
-      case e: Stop => s"stop(${e.clock.fullName(ctx)}, UInt<1>(1), ${e.ret})"
-      case e: chisel3.internal.firrtl.Printf =>
-        val (fmt, args) = e.pable.unpack(ctx)
-        val printfArgs = Seq(e.clock.fullName(ctx), "UInt<1>(1)",
-          "\"" + printf.format(fmt) + "\"") ++ args
-        (printfArgs mkString ("printf(", ", ", ")")) + s": ${e.name}"
-      case e: Verification[_] =>
-        s"""${e.op}(${e.clock.fullName(ctx)}, ${e.predicate.fullName(ctx)}, UInt<1>(1), "${printf.format(e.message)}") : ${e.name}"""
-      case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"
-      case e: DefInstance => s"inst ${e.name} of ${e.id.name}"
-      case w: WhenBegin =>
-        // When consequences are always indented
-        indent()
-        s"when ${w.pred.fullName(ctx)} :"
-      case w: WhenEnd =>
-        // If a when has no else, the indent level must be reset to the enclosing block
-        unindent()
-        if (!w.hasAlt) { for (i <- 0 until w.firrtlDepth) { unindent() } }
-        s"skip"
-      case a: AltBegin =>
-        // Else blocks are always indented
-        indent()
-        s"else :"
-      case o: OtherwiseEnd =>
-        // Chisel otherwise: ends all FIRRTL associated a Chisel when, resetting indent level
-        for (i <- 0 until o.firrtlDepth) { unindent() }
-        s"skip"
-    }
-    firrtlLine + e.sourceInfo.makeMessage(" " + _)
+  def emit(circuit: Circuit): String = {
+    val fcircuit = Converter.convertLazily(circuit)
+    fir.Serializer.serialize(fcircuit)
   }
-
-  private def emitParam(name: String, p: Param): String = {
-    val str = p match {
-      case IntParam(value) => value.toString
-      case DoubleParam(value) => value.toString
-      case StringParam(str) => "\"" + str + "\""
-      case RawParam(str) => "'" + str + "'"
-    }
-    s"parameter $name = $str"
-  }
-
-  /** Generates the FIRRTL module declaration.
-    */
-  private def moduleDecl(m: Component): String = m.id match {
-    case _: BaseBlackBox => newline + s"extmodule ${m.name} : "
-    case _: RawModule => newline + s"module ${m.name} : "
-  }
-
-  /** Generates the FIRRTL module definition.
-    */
-  private def moduleDefn(m: Component): String = {
-    val body = new StringBuilder
-    withIndent {
-      for (p <- m.ports) {
-        val portDef = m match {
-          case bb: DefBlackBox => emitPort(p, bb.topDir)
-          case mod: DefModule => emitPort(p)
-        }
-        body ++= newline + portDef
-      }
-      body ++= newline
-
-      m match {
-        case bb: DefBlackBox =>
-          // Firrtl extmodule can overrule name
-          body ++= newline + s"defname = ${bb.id.desiredName}"
-          body ++= newline + (bb.params map { case (n, p) => emitParam(n, p) } mkString newline)
-        case mod: DefModule => {
-          // Preprocess whens & elsewhens, marking those that have no alternative
-          val procMod = mod.copy(commands = processWhens(mod.commands))
-          for (cmd <- procMod.commands) { body ++= newline + emit(cmd, procMod)}
-        }
-      }
-      body ++= newline
-    }
-    body.toString()
-  }
-
-  /** Returns the FIRRTL declaration and body of a module, or nothing if it's a
-    * duplicate of something already emitted (on the basis of simple string
-    * matching).
-    */
-  private def emit(m: Component): String = {
-    // Generate the body.
-    val sb = new StringBuilder
-    sb.append(moduleDecl(m))
-    sb.append(moduleDefn(m))
-    sb.result
-  }
-
-  /** Preprocess the command queue, marking when/elsewhen statements
-    * that have no alternatives (elsewhens or otherwise). These
-    * alternative-free statements reset the indent level to the
-    * enclosing block upon emission.
-    */
-  private def processWhens(cmds: Seq[Command]): Seq[Command] = {
-    if (cmds.isEmpty) {
-      Seq.empty
-    } else {
-      cmds.zip(cmds.tail).map{
-        case (a: WhenEnd, b: AltBegin) => a.copy(hasAlt = true)
-        case (a, b) => a
-      } ++ cmds.lastOption
-    }
-  }
-
-  private var indentLevel = 0
-  private def newline = "\n" + ("  " * indentLevel)
-  private def indent(): Unit = indentLevel += 1
-  private def unindent() { require(indentLevel > 0); indentLevel -= 1 }
-  private def withIndent(f: => Unit) { indent(); f; unindent() }
-
-  private val res = new StringBuilder()
-  res ++= s";${BuildInfo.toString}\n"
-  res ++= s"circuit ${circuit.name} : "
-  withIndent { circuit.components.foreach(c => res ++= emit(c)) }
-  res ++= newline
 }
+
-- 
cgit v1.2.3


From d9c30ea0fdd90f3e47cae161f4a7224a861a6bf0 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 20 Aug 2021 12:00:08 -0700
Subject: Emit .fir lazily, overcomes JVM 2 GiB String limit

---
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

(limited to 'src/main/scala/chisel3/internal')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 53329908..a94558ce 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -1,12 +1,23 @@
 // SPDX-License-Identifier: Apache-2.0
 
 package chisel3.internal.firrtl
-import firrtl.{ir => fir}
+
+import scala.collection.immutable.LazyList // Needed for 2.12 alias
+import firrtl.ir.Serializer
 
 private[chisel3] object Emitter {
   def emit(circuit: Circuit): String = {
     val fcircuit = Converter.convertLazily(circuit)
-    fir.Serializer.serialize(fcircuit)
+    Serializer.serialize(fcircuit)
+  }
+
+  def emitLazily(circuit: Circuit): Iterable[String] = {
+    val result = LazyList(s"circuit ${circuit.name} :\n")
+    val modules = circuit.components.view.map(Converter.convert)
+    val moduleStrings = modules.flatMap { m =>
+      Array(Serializer.serialize(m, 1), "\n\n")
+    }
+    result ++ moduleStrings
   }
 }
 
-- 
cgit v1.2.3