From 2d4cb434f214c31b5e3e4247775b27f1eb8d7734 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 25 Jul 2016 09:18:23 -0700 Subject: Add missing compatibility.scala. --- src/main/scala/chisel3/compatibility.scala | 156 +++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 src/main/scala/chisel3/compatibility.scala (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala new file mode 100644 index 00000000..9360acbc --- /dev/null +++ b/src/main/scala/chisel3/compatibility.scala @@ -0,0 +1,156 @@ +// See LICENSE for license details. + +// Allows legacy users to continue using Chisel (capital C) package name while +// moving to the more standard package naming convention chisel3 (lowercase c). + +package object Chisel { + type Direction = chisel3.core.Direction + val INPUT = chisel3.core.Direction.Input + val OUTPUT = chisel3.core.Direction.Output + object Flipped { + def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target) + } + type ChiselException = chisel3.internal.ChiselException + + type Data = chisel3.core.Data + val Wire = chisel3.core.Wire + val Clock = chisel3.core.Clock + type Clock = chisel3.core.Clock + + type Aggregate = chisel3.core.Aggregate + val Vec = chisel3.core.Vec + type Vec[T <: Data] = chisel3.core.Vec[T] + type VecLike[T <: Data] = chisel3.core.VecLike[T] + type Bundle = chisel3.core.Bundle + + val assert = chisel3.core.assert + val stop = chisel3.core.stop + + type Element = chisel3.core.Element + type Bits = chisel3.core.Bits + val Bits = chisel3.core.Bits + type Num[T <: Data] = chisel3.core.Num[T] + type UInt = chisel3.core.UInt + val UInt = chisel3.core.UInt + type SInt = chisel3.core.SInt + val SInt = chisel3.core.SInt + type Bool = chisel3.core.Bool + val Bool = chisel3.core.Bool + val Mux = chisel3.core.Mux + + type BlackBox = chisel3.core.BlackBox + + val Mem = chisel3.core.Mem + type MemBase[T <: Data] = chisel3.core.MemBase[T] + type Mem[T <: Data] = chisel3.core.Mem[T] + val SeqMem = chisel3.core.SeqMem + type SeqMem[T <: Data] = chisel3.core.SeqMem[T] + + val Module = chisel3.core.Module + type Module = chisel3.core.Module + + val printf = chisel3.core.printf + + val Reg = chisel3.core.Reg + + val when = chisel3.core.when + type WhenContext = chisel3.core.WhenContext + + + type BackendCompilationUtilities = chisel3.BackendCompilationUtilities + val Driver = chisel3.Driver + type FileSystemUtilities = chisel3.compatibility.FileSystemUtilities + val ImplicitConversions = chisel3.util.ImplicitConversions + val chiselMain = chisel3.compatibility.chiselMain + val throwException = chisel3.compatibility.throwException + val debug = chisel3.core.debug + + object testers { + type BasicTester = chisel3.testers.BasicTester + val TesterDriver = chisel3.testers.TesterDriver + } + + + val log2Up = chisel3.util.log2Up + val log2Ceil = chisel3.util.log2Ceil + val log2Down = chisel3.util.log2Down + val log2Floor = chisel3.util.log2Floor + val isPow2 = chisel3.util.isPow2 + + val BitPat = chisel3.util.BitPat + type BitPat = chisel3.util.BitPat + + type ArbiterIO[T <: Data] = chisel3.util.ArbiterIO[T] + type LockingArbiterLike[T <: Data] = chisel3.util.LockingArbiterLike[T] + type LockingRRArbiter[T <: Data] = chisel3.util.LockingRRArbiter[T] + type LockingArbiter[T <: Data] = chisel3.util.LockingArbiter[T] + type RRArbiter[T <: Data] = chisel3.util.RRArbiter[T] + type Arbiter[T <: Data] = chisel3.util.Arbiter[T] + + val FillInterleaved = chisel3.util.FillInterleaved + val PopCount = chisel3.util.PopCount + val Fill = chisel3.util.Fill + val Reverse = chisel3.util.Reverse + + val Cat = chisel3.util.Cat + + val Log2 = chisel3.util.Log2 + + val unless = chisel3.util.unless + type SwitchContext[T <: Bits] = chisel3.util.SwitchContext[T] + val is = chisel3.util.is + val switch = chisel3.util.switch + + type Counter = chisel3.util.Counter + val Counter = chisel3.util.Counter + + type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T] + val DecoupledIO = chisel3.util.DecoupledIO + object EnqIO { + def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen)) + } + object DeqIO { + def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen) + } + type QueueIO[T <: Data] = chisel3.util.QueueIO[T] + type Queue[T <: Data] = chisel3.util.Queue[T] + val Queue = chisel3.util.Queue + + val Enum = chisel3.util.Enum + + val LFSR16 = chisel3.util.LFSR16 + + val ListLookup = chisel3.util.ListLookup + val Lookup = chisel3.util.Lookup + + val Mux1H = chisel3.util.Mux1H + val PriorityMux = chisel3.util.PriorityMux + val MuxLookup = chisel3.util.MuxLookup + val MuxCase = chisel3.util.MuxCase + + val OHToUInt = chisel3.util.OHToUInt + val PriorityEncoder = chisel3.util.PriorityEncoder + val UIntToOH = chisel3.util.UIntToOH + val PriorityEncoderOH = chisel3.util.PriorityEncoderOH + + val RegNext = chisel3.util.RegNext + val RegInit = chisel3.util.RegInit + val RegEnable = chisel3.util.RegEnable + val ShiftRegister = chisel3.util.ShiftRegister + + type ValidIO[+T <: Data] = chisel3.util.Valid[T] + val Valid = chisel3.util.Valid + val Pipe = chisel3.util.Pipe + type Pipe[T <: Data] = chisel3.util.Pipe[T] + + + import chisel3.internal.firrtl.Width + implicit def fromBigIntToLiteral(x: BigInt): chisel3.fromBigIntToLiteral = + new chisel3.fromBigIntToLiteral(x) + implicit def fromIntToLiteral(x: Int): chisel3.fromIntToLiteral= + new chisel3.fromIntToLiteral(x) + implicit def fromStringToLiteral(x: String): chisel3.fromStringToLiteral= + new chisel3.fromStringToLiteral(x) + implicit def fromBooleanToLiteral(x: Boolean): chisel3.fromBooleanToLiteral= + new chisel3.fromBooleanToLiteral(x) +} -- cgit v1.2.3 From 7aa05590382b0528799ad5e9f1318ce42e409793 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 25 Jul 2016 14:06:51 -0700 Subject: Minimize differences with master. Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. --- src/main/scala/chisel3/compatibility.scala | 1 + 1 file changed, 1 insertion(+) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index b7020b5e..041553e0 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -7,6 +7,7 @@ package object Chisel { type Direction = chisel3.core.Direction val INPUT = chisel3.core.Direction.Input val OUTPUT = chisel3.core.Direction.Output + val NODIR = chisel3.core.Direction.Unspecified object Flipped { def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target) } -- cgit v1.2.3 From ddeff65c1c50f0a7c3604cdc254538fbf1263d4f Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 27 Jul 2016 09:13:15 -0700 Subject: Correct EnqIO/DeqIO Flipped-ness. --- src/main/scala/chisel3/compatibility.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 041553e0..3b613a5e 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -108,10 +108,10 @@ package object Chisel { type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T] val DecoupledIO = chisel3.util.DecoupledIO object EnqIO { - def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen)) + def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen) } object DeqIO { - def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen) + def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen)) } type QueueIO[T <: Data] = chisel3.util.QueueIO[T] type Queue[T <: Data] = chisel3.util.Queue[T] -- cgit v1.2.3 From 138329479914ac37b49a5a44841dc1de2929dca5 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 27 Jul 2016 10:36:55 -0700 Subject: More compatibility fixes --- src/main/scala/chisel3/compatibility.scala | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 3b613a5e..a7968bd5 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -107,6 +107,19 @@ package object Chisel { type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T] val DecoupledIO = chisel3.util.DecoupledIO + class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) { + def init(): Unit = { + this.noenq() + } + override def cloneType: this.type = EnqIO(gen).asInstanceOf[this.type] + } + class DeqIO[+T <: Data](gen: T) extends DecoupledIO(gen) { + chisel3.core.Binding.bind(this, chisel3.core.FlippedBinder, "Error: Cannot flip ") + def init(): Unit = { + this.nodeq() + } + override def cloneType: this.type = DeqIO(gen).asInstanceOf[this.type] + } object EnqIO { def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen) } -- cgit v1.2.3 From 81d60a4076eab24553f67ae6b85031d2075a5fac Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 28 Jul 2016 17:20:33 -0700 Subject: Add missing Decoupled object pointer. --- src/main/scala/chisel3/compatibility.scala | 1 + 1 file changed, 1 insertion(+) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index a7968bd5..939e005a 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -107,6 +107,7 @@ package object Chisel { type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T] val DecoupledIO = chisel3.util.DecoupledIO + val Decoupled = chisel3.util.DecoupledIO class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) { def init(): Unit = { this.noenq() -- cgit v1.2.3 From c661d9c8def3a14e9e8a42d96005ead78e11e34d Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 3 Aug 2016 13:57:03 -0700 Subject: Merge "package" code into "compatibility". --- src/main/scala/chisel3/compatibility.scala | 50 ++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 10 deletions(-) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 939e005a..d4ad7b9f 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -57,6 +57,46 @@ package object Chisel { val when = chisel3.core.when type WhenContext = chisel3.core.WhenContext + import chisel3.internal.firrtl.Width + /** + * These implicit classes allow one to convert scala.Int|scala.BigInt to + * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. + * The versions .asUInt(width)|.asSInt(width) are also available to explicitly + * mark a width for the new literal. + * + * Also provides .asBool to scala.Boolean and .asUInt to String + * + * Note that, for stylistic reasons, one should avoid extracting immediately + * after this call using apply, ie. 0.asUInt(1)(0) due to potential for + * confusion (the 1 is a bit length and the 0 is a bit extraction position). + * Prefer storing the result and then extracting from it. + */ + implicit class fromIntToLiteral(val x: Int) extends AnyVal { + def U: UInt = UInt(BigInt(x), Width()) + def S: SInt = SInt(BigInt(x), Width()) + + def asUInt() = UInt(x, Width()) + def asSInt() = SInt(x, Width()) + def asUInt(width: Int) = UInt(x, width) + def asSInt(width: Int) = SInt(x, width) + } + + implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { + def U: UInt = UInt(x, Width()) + def S: SInt = SInt(x, Width()) + + def asUInt() = UInt(x, Width()) + def asSInt() = SInt(x, Width()) + def asUInt(width: Int) = UInt(x, width) + def asSInt(width: Int) = SInt(x, width) + } + implicit class fromStringToLiteral(val x: String) extends AnyVal { + def U: UInt = UInt(x) + } + implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { + def B: Bool = Bool(x) + } + type BackendCompilationUtilities = chisel3.BackendCompilationUtilities val Driver = chisel3.Driver @@ -158,14 +198,4 @@ package object Chisel { val Pipe = chisel3.util.Pipe type Pipe[T <: Data] = chisel3.util.Pipe[T] - - import chisel3.internal.firrtl.Width - implicit def fromBigIntToLiteral(x: BigInt): chisel3.fromBigIntToLiteral = - new chisel3.fromBigIntToLiteral(x) - implicit def fromIntToLiteral(x: Int): chisel3.fromIntToLiteral= - new chisel3.fromIntToLiteral(x) - implicit def fromStringToLiteral(x: String): chisel3.fromStringToLiteral= - new chisel3.fromStringToLiteral(x) - implicit def fromBooleanToLiteral(x: Boolean): chisel3.fromBooleanToLiteral= - new chisel3.fromBooleanToLiteral(x) } -- cgit v1.2.3 From 35c8e40b25f529da883e8ae91644fcc496e087da Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 22 Aug 2016 16:57:43 -0700 Subject: Purely cosmetic changes to placate the scalastyle checker. --- src/main/scala/chisel3/compatibility.scala | 34 +++++++++++++++--------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 5624b79c..35c44330 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -3,7 +3,7 @@ // Allows legacy users to continue using Chisel (capital C) package name while // moving to the more standard package naming convention chisel3 (lowercase c). -package object Chisel { +package object Chisel { // scalastyle:ignore package.object.name type Direction = chisel3.core.Direction val INPUT = chisel3.core.Direction.Input val OUTPUT = chisel3.core.Direction.Output @@ -72,29 +72,29 @@ package object Chisel { * Prefer storing the result and then extracting from it. */ implicit class fromIntToLiteral(val x: Int) extends AnyVal { - def U: UInt = UInt(BigInt(x), Width()) - def S: SInt = SInt(BigInt(x), Width()) + def U: UInt = UInt(BigInt(x), Width()) // scalastyle:ignore method.name + def S: SInt = SInt(BigInt(x), Width()) // scalastyle:ignore method.name - def asUInt() = UInt(x, Width()) - def asSInt() = SInt(x, Width()) - def asUInt(width: Int) = UInt(x, width) - def asSInt(width: Int) = SInt(x, width) + def asUInt(): UInt = UInt(x, Width()) + def asSInt(): SInt = SInt(x, Width()) + def asUInt(width: Int): UInt = UInt(x, width) + def asSInt(width: Int): SInt = SInt(x, width) } - + implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { - def U: UInt = UInt(x, Width()) - def S: SInt = SInt(x, Width()) + def U: UInt = UInt(x, Width()) // scalastyle:ignore method.name + def S: SInt = SInt(x, Width()) // scalastyle:ignore method.name - def asUInt() = UInt(x, Width()) - def asSInt() = SInt(x, Width()) - def asUInt(width: Int) = UInt(x, width) - def asSInt(width: Int) = SInt(x, width) + def asUInt(): UInt = UInt(x, Width()) + def asSInt(): SInt = SInt(x, Width()) + def asUInt(width: Int): UInt = UInt(x, width) + def asSInt(width: Int): SInt = SInt(x, width) } implicit class fromStringToLiteral(val x: String) extends AnyVal { - def U: UInt = UInt(x) + def U: UInt = UInt(x) // scalastyle:ignore method.name } implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { - def B: Bool = Bool(x) + def B: Bool = Bool(x) // scalastyle:ignore method.name } @@ -105,7 +105,7 @@ package object Chisel { val throwException = chisel3.compatibility.throwException val debug = chisel3.compatibility.debug - object testers { + object testers { // scalastyle:ignore object.name type BasicTester = chisel3.testers.BasicTester val TesterDriver = chisel3.testers.TesterDriver } -- cgit v1.2.3 From 1973e4d7333e2c57be4bcb7204210ecafdacab93 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 29 Aug 2016 17:04:51 -0700 Subject: Check module-specific compile options. Import chisel3.NotStrict.CompileOptions in Chisel package. Add CompileOptions tests. --- src/main/scala/chisel3/compatibility.scala | 1 + 1 file changed, 1 insertion(+) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 35c44330..8524ea2a 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -4,6 +4,7 @@ // moving to the more standard package naming convention chisel3 (lowercase c). package object Chisel { // scalastyle:ignore package.object.name + import chisel3.NotStrict.CompileOptions type Direction = chisel3.core.Direction val INPUT = chisel3.core.Direction.Input val OUTPUT = chisel3.core.Direction.Output -- cgit v1.2.3 From 8002f7ac6731b1da5e0d8e7b1536995a23878037 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 30 Aug 2016 13:45:37 -0700 Subject: Make compileOptions in the Chisel package effective. Remove references to the Chisel package in favor of explicit chisel3 imports in tests, --- src/main/scala/chisel3/compatibility.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 8524ea2a..85311ba2 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -4,7 +4,7 @@ // moving to the more standard package naming convention chisel3 (lowercase c). package object Chisel { // scalastyle:ignore package.object.name - import chisel3.NotStrict.CompileOptions + implicit val compileOptions = chisel3.NotStrict.CompileOptions type Direction = chisel3.core.Direction val INPUT = chisel3.core.Direction.Input val OUTPUT = chisel3.core.Direction.Output -- cgit v1.2.3 From 3451ac840b3008597a6905c21d0e77ed613d5dbd Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Fri, 2 Sep 2016 17:07:32 -0700 Subject: Rename implicit compileOptions to defaultCompileOptions. --- src/main/scala/chisel3/compatibility.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 85311ba2..49b8bb2c 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -4,7 +4,7 @@ // moving to the more standard package naming convention chisel3 (lowercase c). package object Chisel { // scalastyle:ignore package.object.name - implicit val compileOptions = chisel3.NotStrict.CompileOptions + implicit val defaultCompileOptions = chisel3.NotStrict.CompileOptions type Direction = chisel3.core.Direction val INPUT = chisel3.core.Direction.Input val OUTPUT = chisel3.core.Direction.Output -- cgit v1.2.3 From 6d8acee760c8c41fcae2ab252161bac96e6954dc Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Fri, 16 Sep 2016 09:07:15 -0700 Subject: Rename DecoupledIO object to Decoupled (compatibility). --- src/main/scala/chisel3/compatibility.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 49b8bb2c..3b1b5b0a 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -146,8 +146,8 @@ package object Chisel { // scalastyle:ignore package.object.name val Counter = chisel3.util.Counter type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T] - val DecoupledIO = chisel3.util.DecoupledIO - val Decoupled = chisel3.util.DecoupledIO + val DecoupledIO = chisel3.util.Decoupled + val Decoupled = chisel3.util.Decoupled class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) { def init(): Unit = { this.noenq() -- cgit v1.2.3 From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 29 Sep 2016 11:44:09 -0700 Subject: Massive rename of CompileOptions. Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports. NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence). We should really thread the CompileOptions through the macro system so the client's implicits are used. --- src/main/scala/chisel3/compatibility.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 3b1b5b0a..646fc84e 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -4,7 +4,7 @@ // moving to the more standard package naming convention chisel3 (lowercase c). package object Chisel { // scalastyle:ignore package.object.name - implicit val defaultCompileOptions = chisel3.NotStrict.CompileOptions + implicit val defaultCompileOptions = chisel3.ExplicitCompileOptions.NotStrict type Direction = chisel3.core.Direction val INPUT = chisel3.core.Direction.Input val OUTPUT = chisel3.core.Direction.Output -- cgit v1.2.3 From 96fb6a5e2c781b20470d02eac186b1b129c20bdf Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 29 Sep 2016 14:57:42 -0700 Subject: Consolidate CompileOptions and re-enable NotStrict pending macro work. --- src/main/scala/chisel3/compatibility.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 646fc84e..aad15f60 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -4,7 +4,7 @@ // moving to the more standard package naming convention chisel3 (lowercase c). package object Chisel { // scalastyle:ignore package.object.name - implicit val defaultCompileOptions = chisel3.ExplicitCompileOptions.NotStrict + implicit val defaultCompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict type Direction = chisel3.core.Direction val INPUT = chisel3.core.Direction.Input val OUTPUT = chisel3.core.Direction.Output -- cgit v1.2.3 From 058711230d2d9976ce35edc2587b17d2d6d58cff Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Fri, 30 Sep 2016 11:28:34 -0700 Subject: Add Data dir method to Chisel compatibility layer. --- src/main/scala/chisel3/compatibility.scala | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/main/scala/chisel3/compatibility.scala') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index aad15f60..d13fcb06 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -12,6 +12,16 @@ package object Chisel { // scalastyle:ignore package.object.name object Flipped { def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target) } + // TODO: Possibly move the AddDirectionToData class here? + implicit class AddDirMethodToData[T<:Data](val target: T) extends AnyVal { + def dir: Direction = { + target match { + case e: Element => e.dir + case _ => chisel3.core.Direction.Unspecified + } + } + } + type ChiselException = chisel3.internal.ChiselException type Data = chisel3.core.Data -- cgit v1.2.3