From 29f84617ea30c7dd30c9616bcdb9a1894b8a0762 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 15:23:25 -0800
Subject: Eliminate some doc warnings

---
 src/main/scala/chisel3/Driver.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/chisel3/Driver.scala')

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index a0713379..11a447d1 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -95,7 +95,7 @@ trait BackendCompilationUtilities {
   /** Generates a Verilator invocation to convert Verilog sources to C++
     * simulation sources.
     *
-    * The Verilator prefix will be V$dutFile, and running this will generate
+    * The Verilator prefix will be V\$dutFile, and running this will generate
     * C++ sources and headers as well as a makefile to compile them.
     *
     * @param dutFile name of the DUT .v without the .v extension
-- 
cgit v1.2.3


From 6929ca0fc64b562f4852a49df617a1836e083563 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Thu, 27 Oct 2016 14:01:33 -0700
Subject: Change Verilator invocation to use O1

Workaround for:
http://www.veripool.org/issues/1101-Verilator-Fix-SmallName-for-ParamTypeDType
---
 src/main/scala/chisel3/Driver.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main/scala/chisel3/Driver.scala')

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 11a447d1..ab51ad25 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -119,13 +119,13 @@ trait BackendCompilationUtilities {
         "-Wno-WIDTH",
         "-Wno-STMTDLY",
         "--trace",
-        "-O0",
+        "-O1",
         "--top-module", topModule,
         "+define+TOP_TYPE=V" + dutFile,
         s"+define+PRINTF_COND=!$topModule.reset",
         s"+define+STOP_COND=!$topModule.reset",
         "-CFLAGS",
-        s"""-Wno-undefined-bool-conversion -O0 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
+        s"""-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
         "-Mdir", dir.toString,
         "--exe", cppHarness.toString)
     System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex
-- 
cgit v1.2.3


From ad53161bbb9f67e16b88ca7a508a537f88d77e05 Mon Sep 17 00:00:00 2001
From: Chick Markley
Date: Wed, 7 Dec 2016 10:31:23 -0800
Subject: Support for creating chisel annotations that are consumed by firrtl
 (#393)

* Support for creating chisel annotations that are consumed by firrtl
Update annotation serialization in Driver
Add DiamondAnnotation Spec that illustrates how to do simple annotations
frontEnd must have dependency on firrtl
Add annotation method to Module
Circuit has extra optional parameter that is Seq of Annotations
In Builder add annotation buffer to DynamicContext to store annotations created in modules
Added explicit types on naming api methods to avoid type confusion
Because some names are not available until elaboration create intermediate ChiselAnnotation that
gets turned into a firrtl Annotation after elaboration
In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though
intermediate file .fir and .anno files are still created for inspection and/or later use

* Somehow missed ChiselAnnotation

* fixes for Jack's review of PR
---
 src/main/scala/chisel3/Driver.scala | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/main/scala/chisel3/Driver.scala')

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index ab51ad25..646702c3 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -6,10 +6,13 @@ import chisel3.internal.firrtl.Emitter
 
 import scala.sys.process._
 import java.io._
+import net.jcazevedo.moultingyaml._
 
 import internal.firrtl._
 import firrtl._
 
+import _root_.firrtl.annotations.AnnotationYamlProtocol._
+
 /**
   * The Driver provides methods to invoke the chisel3 compiler and the firrtl compiler.
   * By default firrtl is automatically run after chisel.  an [[ExecutionOptionsManager]]
@@ -239,6 +242,15 @@ object Driver extends BackendCompilationUtilities {
     w.write(firrtlString)
     w.close()
 
+    val annotationFile = new File(optionsManager.getBuildFileName("anno"))
+    val af = new FileWriter(annotationFile)
+    af.write(circuit.annotations.toArray.toYaml.prettyPrint)
+    af.close()
+
+    /* This passes the firrtl source and annotations directly to firrtl */
+    optionsManager.firrtlOptions = optionsManager.firrtlOptions.copy(
+      firrtlSource = Some(firrtlString), annotations = circuit.annotations.toList)
+
     val firrtlExecutionResult = if(chiselOptions.runFirrtlCompiler) {
       Some(firrtl.Driver.execute(optionsManager))
     }
-- 
cgit v1.2.3