From f36524e388b060b1bb535ae21cb1bcbbea220be9 Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 20 May 2016 18:09:57 -0700
Subject: Rename packages to lowercase chisel, add compatibility layer

---
 src/main/scala/chisel/util/Bitwise.scala | 71 ++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 src/main/scala/chisel/util/Bitwise.scala

(limited to 'src/main/scala/chisel/util/Bitwise.scala')

diff --git a/src/main/scala/chisel/util/Bitwise.scala b/src/main/scala/chisel/util/Bitwise.scala
new file mode 100644
index 00000000..27064059
--- /dev/null
+++ b/src/main/scala/chisel/util/Bitwise.scala
@@ -0,0 +1,71 @@
+// See LICENSE for license details.
+
+/** Miscellaneous circuit generators operating on bits.
+  */
+
+package chisel
+
+object FillInterleaved
+{
+  def apply(n: Int, in: UInt): UInt = apply(n, in.toBools)
+  def apply(n: Int, in: Seq[Bool]): UInt = Vec(in.map(Fill(n, _))).toBits
+}
+
+/** Returns the number of bits set (i.e value is 1) in the input signal.
+  */
+object PopCount
+{
+  def apply(in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq)
+  def apply(in: Bits): UInt = apply((0 until in.getWidth).map(in(_)))
+}
+
+/** Fill fans out a UInt to multiple copies */
+object Fill {
+  /** Fan out x n times */
+  def apply(n: Int, x: UInt): UInt = {
+    n match {
+      case 0 => UInt(width=0)
+      case 1 => x
+      case y if n > 1 =>
+        val p2 = Array.ofDim[UInt](log2Up(n + 1))
+        p2(0) = x
+        for (i <- 1 until p2.length)
+          p2(i) = Cat(p2(i-1), p2(i-1))
+        Cat((0 until log2Up(y + 1)).filter(i => (y & (1 << i)) != 0).map(p2(_)))
+      case _ => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.")
+    }
+  }
+  /** Fan out x n times */
+  def apply(n: Int, x: Bool): UInt =
+    if (n > 1) {
+      UInt(0,n) - x
+    } else {
+      apply(n, x: UInt)
+    }
+}
+
+/** Litte/big bit endian convertion: reverse the order of the bits in a UInt.
+*/
+object Reverse
+{
+  private def doit(in: UInt, length: Int): UInt = {
+    if (length == 1) {
+      in
+    } else if (isPow2(length) && length >= 8 && length <= 64) {
+      // This esoterica improves simulation performance
+      var res = in
+      var shift = length >> 1
+      var mask = UInt((BigInt(1) << length) - 1, length)
+      do {
+        mask = mask ^ (mask(length-shift-1,0) << shift)
+        res = ((res >> shift) & mask) | ((res(length-shift-1,0) << shift) & ~mask)
+        shift = shift >> 1
+      } while (shift > 0)
+      res
+    } else {
+      val half = (1 << log2Up(length))/2
+      Cat(doit(in(half-1,0), half), doit(in(length-1,half), length-half))
+    }
+  }
+  def apply(in: UInt): UInt = doit(in, in.getWidth)
+}
-- 
cgit v1.2.3


From 881ac3cb3a9da0c7827a161238468df4727996f0 Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 27 May 2016 13:24:36 -0700
Subject: Move utils into utils

---
 src/main/scala/chisel/util/Bitwise.scala | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src/main/scala/chisel/util/Bitwise.scala')

diff --git a/src/main/scala/chisel/util/Bitwise.scala b/src/main/scala/chisel/util/Bitwise.scala
index 27064059..94413fc7 100644
--- a/src/main/scala/chisel/util/Bitwise.scala
+++ b/src/main/scala/chisel/util/Bitwise.scala
@@ -3,7 +3,9 @@
 /** Miscellaneous circuit generators operating on bits.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 object FillInterleaved
 {
-- 
cgit v1.2.3


From 69c984607e87cb62c82c99056b2664f11b968267 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 1 Jun 2016 12:46:05 -0700
Subject: Package split chisel core

---
 src/main/scala/chisel/util/Bitwise.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/main/scala/chisel/util/Bitwise.scala')

diff --git a/src/main/scala/chisel/util/Bitwise.scala b/src/main/scala/chisel/util/Bitwise.scala
index 94413fc7..d7d62ea3 100644
--- a/src/main/scala/chisel/util/Bitwise.scala
+++ b/src/main/scala/chisel/util/Bitwise.scala
@@ -6,6 +6,7 @@
 package chisel.util
 
 import chisel._
+import chisel.core.SeqUtils
 
 object FillInterleaved
 {
-- 
cgit v1.2.3