From 3ea058aff4eef3fc7ed928fcaf848eb9dff7f702 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Thu, 30 Jul 2015 18:21:06 -0700
Subject: Work around FIRRTL literal restrictions

---
 src/main/scala/Chisel/Core.scala | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'src/main/scala/Chisel')

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 96ac04da..354f3ac1 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -177,14 +177,17 @@ abstract class LitArg (val num: BigInt, val width: Int) extends Arg {
 
 case class ULit(n: BigInt, w: Int = -1) extends LitArg(n, w) {
   def fullname = name
-  def name = "UInt<" + width + ">(" + num + ")"
+  def name = "UInt<" + width + ">(\"h0" + num.toString(16) + "\")"
 
   require(n >= 0, s"UInt literal ${n} is negative")
 }
 
 case class SLit(n: BigInt, w: Int = -1) extends LitArg(n, w) {
   def fullname = name
-  def name = "SInt<" + width + ">(" + num + ")"
+  def name = {
+    val unsigned = if (n < 0) (BigInt(1) << w) + n else n
+    s"asSInt(${ULit(unsigned, w).name})"
+  }
 }
 
 case class Ref(val name: String) extends Immediate {
-- 
cgit v1.2.3