From cd016b42a0c940f671bdd3c117b8f0ae3c4b30b5 Mon Sep 17 00:00:00 2001 From: ducky Date: Wed, 9 Dec 2015 14:18:46 -0800 Subject: Extend TesterDriver to optionally take in additional Verilog sources --- src/main/scala/Chisel/testers/TesterDriver.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/main/scala/Chisel/testers') diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala index d104782a..4c6134f0 100644 --- a/src/main/scala/Chisel/testers/TesterDriver.scala +++ b/src/main/scala/Chisel/testers/TesterDriver.scala @@ -29,7 +29,7 @@ object TesterDriver extends BackendCompilationUtilities with FileSystemUtilities // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe if (((new File(System.getProperty("user.dir") + "/src/main/resources/top.cpp") #> cppHarness) #&& firrtlToVerilog(prefix, dir) #&& - verilogToCpp(prefix, dir, vDut, cppHarness, vH) #&& + verilogToCpp(prefix, dir, vDut, Seq(), cppHarness, vH) #&& cppToExe(prefix, dir)).! == 0) { executeExpectingSuccess(prefix, dir) } else { -- cgit v1.2.3 From 996ea685649136229b62579bdc1aecdb7e14d4dc Mon Sep 17 00:00:00 2001 From: ducky Date: Wed, 9 Dec 2015 14:48:25 -0800 Subject: Optional additional Verilog sources to include in execute --- src/main/scala/Chisel/testers/TesterDriver.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/main/scala/Chisel/testers') diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala index 4c6134f0..90dc9355 100644 --- a/src/main/scala/Chisel/testers/TesterDriver.scala +++ b/src/main/scala/Chisel/testers/TesterDriver.scala @@ -8,7 +8,7 @@ import java.io.File object TesterDriver extends BackendCompilationUtilities with FileSystemUtilities { /** For use with modules that should successfully be elaborated by the * frontend, and which can be turned into executeables with assertions. */ - def execute(t: () => BasicTester): Boolean = { + def execute(t: () => BasicTester, additionalVSources: Seq[File] = Seq()): Boolean = { // Invoke the chisel compiler to get the circuit's IR val circuit = Driver.elaborate(t) @@ -29,7 +29,7 @@ object TesterDriver extends BackendCompilationUtilities with FileSystemUtilities // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe if (((new File(System.getProperty("user.dir") + "/src/main/resources/top.cpp") #> cppHarness) #&& firrtlToVerilog(prefix, dir) #&& - verilogToCpp(prefix, dir, vDut, Seq(), cppHarness, vH) #&& + verilogToCpp(prefix, dir, vDut, additionalVSources, cppHarness, vH) #&& cppToExe(prefix, dir)).! == 0) { executeExpectingSuccess(prefix, dir) } else { -- cgit v1.2.3 From 2785c3337a323e343141fd6a7fe4d2468e7feb34 Mon Sep 17 00:00:00 2001 From: ducky Date: Wed, 9 Dec 2015 17:21:38 -0800 Subject: Refactor testharness generation to create directories and have minimal API --- src/main/scala/Chisel/testers/TesterDriver.scala | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) (limited to 'src/main/scala/Chisel/testers') diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala index 90dc9355..364480a7 100644 --- a/src/main/scala/Chisel/testers/TesterDriver.scala +++ b/src/main/scala/Chisel/testers/TesterDriver.scala @@ -5,7 +5,7 @@ import Chisel._ import scala.sys.process._ import java.io.File -object TesterDriver extends BackendCompilationUtilities with FileSystemUtilities { +object TesterDriver extends BackendCompilationUtilities { /** For use with modules that should successfully be elaborated by the * frontend, and which can be turned into executeables with assertions. */ def execute(t: () => BasicTester, additionalVSources: Seq[File] = Seq()): Boolean = { @@ -15,23 +15,20 @@ object TesterDriver extends BackendCompilationUtilities with FileSystemUtilities // Set up a bunch of file handlers based on a random temp filename, // plus the quirks of Verilator's naming conventions val target = circuit.name - val fname = File.createTempFile(target, "") - val path = fname.getParentFile.toString + + val path = createTempDirectory(target) + val fname = File.createTempFile(target, "", path) val prefix = fname.toString.split("/").last - val dir = new File(System.getProperty("java.io.tmpdir")) - val vDut = new File(fname.toString + ".v") - val vH = new File(path + "/V" + prefix + ".h") - val cppHarness = new File(fname.toString + ".cpp") + val cppHarness = new File(System.getProperty("user.dir") + "/src/main/resources/top.cpp") // For now, dump the IR out to a file Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir"))) // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe - if (((new File(System.getProperty("user.dir") + "/src/main/resources/top.cpp") #> cppHarness) #&& - firrtlToVerilog(prefix, dir) #&& - verilogToCpp(prefix, dir, vDut, additionalVSources, cppHarness, vH) #&& - cppToExe(prefix, dir)).! == 0) { - executeExpectingSuccess(prefix, dir) + if ((firrtlToVerilog(prefix, path) #&& + verilogToCpp(prefix, path, additionalVSources, cppHarness) #&& + cppToExe(prefix, path)).! == 0) { + executeExpectingSuccess(prefix, path) } else { false } -- cgit v1.2.3