From 544afdebc4d1b441e57123bd67bc48e8c036ffbb Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Sat, 23 Jan 2016 15:56:55 -0800
Subject: Move firrtl subpackage to inside internal subpackage.

---
 src/main/scala/Chisel/Module.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/Chisel/Module.scala')

diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala
index 05b7dc26..1681f901 100644
--- a/src/main/scala/Chisel/Module.scala
+++ b/src/main/scala/Chisel/Module.scala
@@ -7,7 +7,7 @@ import scala.collection.mutable.{ArrayBuffer, HashSet}
 import internal._
 import internal.Builder.pushCommand
 import internal.Builder.dynamicContext
-import firrtl._
+import internal.firrtl._
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
-- 
cgit v1.2.3


From 86a6c6bcdc349f40dcc31bce1931dc7c427da674 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Sat, 23 Jan 2016 21:11:09 -0800
Subject: Change implicit clock name to clk to match Chisel2

This allows us to share Verilog test harnesses between the two.
---
 src/main/scala/Chisel/Module.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/Chisel/Module.scala')

diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala
index 1681f901..2a0f29db 100644
--- a/src/main/scala/Chisel/Module.scala
+++ b/src/main/scala/Chisel/Module.scala
@@ -60,7 +60,7 @@ abstract class Module(_clock: Clock = null, _reset: Bool = null) extends HasId {
   private[Chisel] def ref = Builder.globalRefMap(this)
   private[Chisel] def lref = ref
 
-  private def ports = (clock, "clock") :: (reset, "reset") :: (io, "io") :: Nil
+  private def ports = (clock, "clk") :: (reset, "reset") :: (io, "io") :: Nil
 
   private[Chisel] def computePorts = ports map { case (port, name) =>
     val bundleDir = if (port.isFlip) INPUT else OUTPUT
-- 
cgit v1.2.3


From 41674d5e130f64d7489fdb8583b8f4ad88b64aeb Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Thu, 28 Jan 2016 12:05:03 -0800
Subject: Use FIRRTL is invalid construct

---
 src/main/scala/Chisel/Module.scala | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

(limited to 'src/main/scala/Chisel/Module.scala')

diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala
index 2a0f29db..463c2f81 100644
--- a/src/main/scala/Chisel/Module.scala
+++ b/src/main/scala/Chisel/Module.scala
@@ -20,16 +20,12 @@ object Module {
   def apply[T <: Module](bc: => T): T = {
     val parent = dynamicContext.currentModule
     val m = bc.setRefs()
-    // init module outputs
-    m._commands prependAll (for (p <- m.io.flatten; if p.dir == OUTPUT)
-      yield Connect(p.lref, p.fromInt(0).ref))
+    m._commands.prepend(DefInvalid(m.io.ref)) // init module outputs
     dynamicContext.currentModule = parent
     val ports = m.computePorts
     Builder.components += Component(m, m.name, ports, m._commands)
     pushCommand(DefInstance(m, ports))
-    // init instance inputs
-    for (p <- m.io.flatten; if p.dir == INPUT)
-      p := p.fromInt(0)
+    pushCommand(DefInvalid(m.io.ref)) // init instance inputs
     m.connectImplicitIOs()
   }
 }
-- 
cgit v1.2.3