From 2ceb98ee2a203e2cb394f3f4b9cf0628e7485f6f Mon Sep 17 00:00:00 2001
From: ducky
Date: Tue, 3 Nov 2015 12:57:58 -0800
Subject: Add documentation on some non-intuitive parts

---
 src/main/scala/Chisel/Mem.scala | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/main/scala/Chisel/Mem.scala')

diff --git a/src/main/scala/Chisel/Mem.scala b/src/main/scala/Chisel/Mem.scala
index 87f717b6..f4003c25 100644
--- a/src/main/scala/Chisel/Mem.scala
+++ b/src/main/scala/Chisel/Mem.scala
@@ -66,6 +66,9 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
   * Writes take effect on the rising clock edge after the request. Reads are
   * combinational (requests will return data on the same cycle).
   * Read-after-write hazards are not an issue.
+  *
+  * @note when multiple conflicting writes are performed on a Mem element, the
+  * result is undefined (unlike Vec, where the last assignment wins)
   */
 sealed class Mem[T <: Data](t: T, length: Int) extends MemBase(t, length)
 
@@ -92,6 +95,9 @@ object SeqMem {
   * data on the rising edge after the request. Read-after-write behavior (when
   * a read and write to the same address are requested on the same cycle) is
   * undefined.
+  *
+  * @note when multiple conflicting writes are performed on a Mem element, the
+  * result is undefined (unlike Vec, where the last assignment wins)
   */
 sealed class SeqMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) {
   def read(addr: UInt, enable: Bool): T =
-- 
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