From f9689cab3bbb5cb2cddbb429bc30d630c886034d Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Tue, 5 Apr 2016 15:19:42 -0700
Subject: Make Wire(init = x) behave the same as Wire(t = x) := x

There's a separate debate to be had about whether we want to
default-initialize Wires to invalid.  This patch just fixes the
implementation of the previous, unsafe approach, which was usually,
but not always, defaulting to invalid.
---
 src/main/scala/Chisel/Data.scala | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

(limited to 'src/main/scala/Chisel/Data.scala')

diff --git a/src/main/scala/Chisel/Data.scala b/src/main/scala/Chisel/Data.scala
index fa6e5729..ac3bd9ab 100644
--- a/src/main/scala/Chisel/Data.scala
+++ b/src/main/scala/Chisel/Data.scala
@@ -123,11 +123,9 @@ object Wire {
   private def makeWire[T <: Data](t: T, init: T): T = {
     val x = Reg.makeType(t, null.asInstanceOf[T], init)
     pushCommand(DefWire(x))
-    if (init != null) {
+    pushCommand(DefInvalid(x.ref))
+    if (init != null)
       x := init
-    } else {
-      pushCommand(DefInvalid(x.ref))
-    }
     x
   }
 }
-- 
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