From 171dd769bebaaeff069ca6dd745d3d1725b36547 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Tue, 12 Jan 2016 16:31:10 -0800
Subject: elaboration-time asserts should call Predef.assert

---
 src/main/scala/Chisel/CoreUtil.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main/scala/Chisel/CoreUtil.scala')

diff --git a/src/main/scala/Chisel/CoreUtil.scala b/src/main/scala/Chisel/CoreUtil.scala
index 7077c9c1..9027711b 100644
--- a/src/main/scala/Chisel/CoreUtil.scala
+++ b/src/main/scala/Chisel/CoreUtil.scala
@@ -43,13 +43,13 @@ object assert {
   /** An elaboration-time assertion, otherwise the same as the above run-time
     * assertion. */
   def apply(cond: Boolean, message: String) {
-    apply(Bool(cond), message)
+    Predef.assert(cond, message)
   }
 
   /** A workaround for default-value overloading problems in Scala, just
     * 'assert(cond, "")' */
   def apply(cond: Boolean) {
-    apply(cond, "")
+    Predef.assert(cond, "")
   }
 }
 
-- 
cgit v1.2.3


From 544afdebc4d1b441e57123bd67bc48e8c036ffbb Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Sat, 23 Jan 2016 15:56:55 -0800
Subject: Move firrtl subpackage to inside internal subpackage.

---
 src/main/scala/Chisel/CoreUtil.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/Chisel/CoreUtil.scala')

diff --git a/src/main/scala/Chisel/CoreUtil.scala b/src/main/scala/Chisel/CoreUtil.scala
index 9027711b..eed90410 100644
--- a/src/main/scala/Chisel/CoreUtil.scala
+++ b/src/main/scala/Chisel/CoreUtil.scala
@@ -4,7 +4,7 @@ package Chisel
 
 import internal._
 import internal.Builder.pushCommand
-import firrtl._
+import internal.firrtl._
 
 object assert {
   /** Checks for a condition to be valid in the circuit at all times. If the
-- 
cgit v1.2.3