From 5293b1cfdcc18a4879f476a1c0370ec19e409089 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Thu, 27 Aug 2015 17:06:49 -0700
Subject: Fix bug where flipping top-level I/O had no effect

The fix is to propagate the flip to the fields in the bundle.
---
 src/main/scala/Chisel/Core.scala | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/main/scala/Chisel/Core.scala')

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 542d31e7..76e45d35 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -805,7 +805,10 @@ abstract class Module(_clock: Clock = null, _reset: Bool = null) extends HasId {
   private[Chisel] def ref = Builder.globalRefMap(this)
   private[Chisel] def lref = ref
 
-  private def computePorts = io.namedElts.unzip._2
+  private[Chisel] def computePorts = io.namedElts.unzip._2 map { x =>
+    val bundleDir = if (io.isFlip ^ x.isFlip) INPUT else OUTPUT
+    Port(x, if (x.dir == NO_DIR) bundleDir else x.dir)
+  }
 
   private def connectImplicitIOs(): this.type = _parent match {
     case Some(p) =>
-- 
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