From 2d7bf7a5fdb5ee722009d4816bb8aa355ead59fc Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Fri, 15 Jan 2016 14:23:28 -0800
Subject: flatten should return Seq[Bits], not Seq[UInt]

Calling toBits inside of flatten makes asInput/asOutput/asDirectionless fail
on SInts.  Also, the abstract type Data was already defining it to return
Seq[Bits], so this change didn't really change the API.
---
 src/main/scala/Chisel/Bits.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/main/scala/Chisel/Bits.scala')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index e001f864..7505c102 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -10,9 +10,7 @@ import firrtl.PrimOp._
 /** Element is a leaf data type: it cannot contain other Data objects. Example
   * uses are for representing primitive data types, like integers and bits.
   */
-abstract class Element(dirArg: Direction, val width: Width) extends Data(dirArg) {
-  private[Chisel] def flatten: IndexedSeq[UInt] = IndexedSeq(toBits)
-}
+abstract class Element(dirArg: Direction, val width: Width) extends Data(dirArg)
 
 /** A data type for values represented by a single bitvector. Provides basic
   * bitwise operations.
@@ -25,6 +23,8 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
 
   private[Chisel] def fromInt(x: BigInt): this.type
 
+  private[Chisel] def flatten: IndexedSeq[Bits] = IndexedSeq(this)
+
   def cloneType: this.type = cloneTypeWidth(width)
 
   override def <> (that: Data): Unit = this := that
-- 
cgit v1.2.3


From fc3587aa24132991a50fbba1fbe4dc769953a3db Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Sat, 16 Jan 2016 18:48:23 -0800
Subject: Disallow Muxing between bundles whose fields have different widths

---
 src/main/scala/Chisel/Bits.scala | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/main/scala/Chisel/Bits.scala')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 7505c102..d6bef0d0 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -538,6 +538,9 @@ object Mux {
   // This returns an lvalue, which it most definitely should not
   private def doWhen[T <: Data](cond: Bool, con: T, alt: T): T = {
     require(con.getClass == alt.getClass, s"can't Mux between ${con.getClass} and ${alt.getClass}")
+    for ((c, a) <- con.flatten zip alt.flatten)
+      require(c.width == a.width, "can't Mux between aggregates of different width")
+
     val res = Wire(t = alt.cloneTypeWidth(con.width max alt.width), init = alt)
     when (cond) { res := con }
     res
-- 
cgit v1.2.3


From 215d71c20e0b3e609eb5ac0f957c475fe3d61357 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Sun, 17 Jan 2016 01:47:58 -0800
Subject: Add =/= operator to BitPat

---
 src/main/scala/Chisel/Bits.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/main/scala/Chisel/Bits.scala')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index d6bef0d0..57d88244 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -321,6 +321,7 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
 
   def === (that: BitPat): Bool = that === this
   def != (that: BitPat): Bool = that != this
+  def =/= (that: BitPat): Bool = that =/= this
 
   /** Returns this UInt as a [[SInt]] with an additional zero in the MSB.
     */
-- 
cgit v1.2.3


From 544afdebc4d1b441e57123bd67bc48e8c036ffbb Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Sat, 23 Jan 2016 15:56:55 -0800
Subject: Move firrtl subpackage to inside internal subpackage.

---
 src/main/scala/Chisel/Bits.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/Chisel/Bits.scala')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 57d88244..b512bb56 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -4,7 +4,7 @@ package Chisel
 
 import internal._
 import internal.Builder.pushOp
-import firrtl._
+import internal.firrtl._
 import firrtl.PrimOp._
 
 /** Element is a leaf data type: it cannot contain other Data objects. Example
-- 
cgit v1.2.3


From b4517e0fb563271464bd40ddf9a46a40fd827da4 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Sat, 23 Jan 2016 16:10:22 -0800
Subject: Don't use deprecated constructs

---
 src/main/scala/Chisel/Bits.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/Chisel/Bits.scala')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index b512bb56..739e6c1b 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -432,7 +432,7 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
   def >= (other: SInt): Bool = compop(GreaterEqOp, other)
   def != (other: SInt): Bool = compop(NotEqualOp, other)
   def === (other: SInt): Bool = compop(EqualOp, other)
-  def abs(): UInt = Mux(this < SInt(0), (-this).toUInt, this.toUInt)
+  def abs(): UInt = Mux(this < SInt(0), (-this).asUInt, this.asUInt)
 
   def << (other: Int): SInt = binop(SInt(this.width + other), ShiftLeftOp, other)
   def << (other: BigInt): SInt = this << other.toInt
-- 
cgit v1.2.3


From 9017ec37d0eb7bb3bd10ed7863c0706ff1020cd9 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Mon, 25 Jan 2016 15:35:03 -0800
Subject: Emit FIRRTL muxes for aggregates

---
 src/main/scala/Chisel/Bits.scala | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

(limited to 'src/main/scala/Chisel/Bits.scala')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 739e6c1b..fbc1586f 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -527,24 +527,20 @@ object Mux {
     case (c: UInt, a: Bool) => doMux(cond, c, a << 0).asInstanceOf[T]
     case (c: Bool, a: UInt) => doMux(cond, c << 0, a).asInstanceOf[T]
     case (c: Bits, a: Bits) => doMux(cond, c, a).asInstanceOf[T]
-    // FIRRTL doesn't support Mux for aggregates, so use a when instead
-    case _ => doWhen(cond, con, alt)
+    case _ => doAggregateMux(cond, con, alt)
   }
 
-  private def doMux[T <: Bits](cond: Bool, con: T, alt: T): T = {
+  private def doMux[T <: Data](cond: Bool, con: T, alt: T): T = {
     require(con.getClass == alt.getClass, s"can't Mux between ${con.getClass} and ${alt.getClass}")
     val d = alt.cloneTypeWidth(con.width max alt.width)
     pushOp(DefPrim(d, MultiplexOp, cond.ref, con.ref, alt.ref))
   }
-  // This returns an lvalue, which it most definitely should not
-  private def doWhen[T <: Data](cond: Bool, con: T, alt: T): T = {
+
+  private def doAggregateMux[T <: Data](cond: Bool, con: T, alt: T): T = {
     require(con.getClass == alt.getClass, s"can't Mux between ${con.getClass} and ${alt.getClass}")
     for ((c, a) <- con.flatten zip alt.flatten)
       require(c.width == a.width, "can't Mux between aggregates of different width")
-
-    val res = Wire(t = alt.cloneTypeWidth(con.width max alt.width), init = alt)
-    when (cond) { res := con }
-    res
+    doMux(cond, con, alt)
   }
 }
 
-- 
cgit v1.2.3


From 71f45a6df99cb86ada1ad9d091a38e01b698a863 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 27 Jan 2016 15:19:23 -0800
Subject: In FIRRTL, bitwise operators return UInt

---
 src/main/scala/Chisel/Bits.scala | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

(limited to 'src/main/scala/Chisel/Bits.scala')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index fbc1586f..3974d05d 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -92,9 +92,6 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   private[Chisel] def redop(op: PrimOp): Bool =
     pushOp(DefPrim(Bool(), op, this.ref))
 
-  /** Returns this wire bitwise-inverted. */
-  def unary_~ : this.type = unop(cloneTypeWidth(width), BitNotOp)
-
   /** Returns this wire zero padded up to the specified width.
     *
     * @note for SInts only, this does sign extension
@@ -292,6 +289,9 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
   def | (other: UInt): UInt = binop(UInt(this.width max other.width), BitOrOp, other)
   def ^ (other: UInt): UInt = binop(UInt(this.width max other.width), BitXorOp, other)
 
+  /** Returns this wire bitwise-inverted. */
+  def unary_~ : UInt = unop(UInt(width = width), BitNotOp)
+
   // REVIEW TODO: Can this be defined on Bits?
   def orR: Bool = this != UInt(0)
   def andR: Bool = ~this === UInt(0)
@@ -422,9 +422,12 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
   def / (other: SInt): SInt = binop(SInt(this.width), DivideOp, other)
   def % (other: SInt): SInt = binop(SInt(this.width), ModOp, other)
 
-  def & (other: SInt): SInt = binop(SInt(this.width max other.width), BitAndOp, other)
-  def | (other: SInt): SInt = binop(SInt(this.width max other.width), BitOrOp, other)
-  def ^ (other: SInt): SInt = binop(SInt(this.width max other.width), BitXorOp, other)
+  def & (other: SInt): SInt = binop(UInt(this.width max other.width), BitAndOp, other).asSInt
+  def | (other: SInt): SInt = binop(UInt(this.width max other.width), BitOrOp, other).asSInt
+  def ^ (other: SInt): SInt = binop(UInt(this.width max other.width), BitXorOp, other).asSInt
+
+  /** Returns this wire bitwise-inverted. */
+  def unary_~ : SInt = unop(UInt(width = width), BitNotOp).asSInt
 
   def < (other: SInt): Bool = compop(LessOp, other)
   def > (other: SInt): Bool = compop(GreaterOp, other)
@@ -490,6 +493,9 @@ sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Wi
   def | (other: Bool): Bool = binop(Bool(), BitOrOp, other)
   def ^ (other: Bool): Bool = binop(Bool(), BitXorOp, other)
 
+  /** Returns this wire bitwise-inverted. */
+  override def unary_~ : Bool = unop(Bool(), BitNotOp)
+
   /** Outputs the logical OR of two Bools.
    */
   def || (that: Bool): Bool = this | that
-- 
cgit v1.2.3


From 22d302ad066d8a073e44289ba4876a165ea56b05 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 27 Jan 2016 15:20:00 -0800
Subject: Remove unsupported FIRRTL node bit(); use bits()

---
 src/main/scala/Chisel/Bits.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/Chisel/Bits.scala')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 3974d05d..6062f2de 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -39,7 +39,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
     if (isLit()) {
       Bool(((litValue() >> x.toInt) & 1) == 1)
     } else {
-      pushOp(DefPrim(Bool(), BitSelectOp, this.ref, ILit(x)))
+      pushOp(DefPrim(Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x)))
     }
   }
 
-- 
cgit v1.2.3


From c9dd94dd6968cba5ecd44fee6df3071cb7a25a9c Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 27 Jan 2016 15:20:44 -0800
Subject: Use FIRRTL node rem, not mod, for %

---
 src/main/scala/Chisel/Bits.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main/scala/Chisel/Bits.scala')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 6062f2de..4a9a6074 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -283,7 +283,7 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
   def * (other: UInt): UInt = binop(UInt(this.width + other.width), TimesOp, other)
   def * (other: SInt): SInt = other * this
   def / (other: UInt): UInt = binop(UInt(this.width), DivideOp, other)
-  def % (other: UInt): UInt = binop(UInt(this.width), ModOp, other)
+  def % (other: UInt): UInt = binop(UInt(this.width), RemOp, other)
 
   def & (other: UInt): UInt = binop(UInt(this.width max other.width), BitAndOp, other)
   def | (other: UInt): UInt = binop(UInt(this.width max other.width), BitOrOp, other)
@@ -420,7 +420,7 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
   def * (other: SInt): SInt = binop(SInt(this.width + other.width), TimesOp, other)
   def * (other: UInt): SInt = binop(SInt(this.width + other.width), TimesOp, other)
   def / (other: SInt): SInt = binop(SInt(this.width), DivideOp, other)
-  def % (other: SInt): SInt = binop(SInt(this.width), ModOp, other)
+  def % (other: SInt): SInt = binop(SInt(this.width), RemOp, other)
 
   def & (other: SInt): SInt = binop(UInt(this.width max other.width), BitAndOp, other).asSInt
   def | (other: SInt): SInt = binop(UInt(this.width max other.width), BitOrOp, other).asSInt
-- 
cgit v1.2.3


From bce4a96934fe8575b71769f2e52a2b75a068d34d Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 27 Jan 2016 15:20:58 -0800
Subject: Use FIRRTL nodes add+tail instead of addw

---
 src/main/scala/Chisel/Bits.scala | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

(limited to 'src/main/scala/Chisel/Bits.scala')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 4a9a6074..b800644d 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -29,6 +29,24 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
 
   override def <> (that: Data): Unit = this := that
 
+  def tail(n: Int): UInt = {
+    val w = width match {
+      case KnownWidth(x) =>
+        require(x >= n, s"Can't tail($n) for width $x < $n")
+        Width(x - n)
+      case UnknownWidth() => Width()
+    }
+    binop(UInt(width = w), TailOp, n)
+  }
+
+  def head(n: Int): UInt = {
+    width match {
+      case KnownWidth(x) => require(x >= n, s"Can't head($n) for width $x < $n")
+      case UnknownWidth() =>
+    }
+    binop(UInt(width = n), HeadOp, n)
+  }
+
   /** Returns the specified bit on this wire as a [[Bool]], statically
     * addressed.
     */
@@ -276,10 +294,10 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
   def unary_-% : UInt = UInt(0) -% this
   def +& (other: UInt): UInt = binop(UInt((this.width max other.width) + 1), AddOp, other)
   def + (other: UInt): UInt = this +% other
-  def +% (other: UInt): UInt = binop(UInt(this.width max other.width), AddModOp, other)
+  def +% (other: UInt): UInt = (this +& other) tail 1
   def -& (other: UInt): UInt = binop(UInt((this.width max other.width) + 1), SubOp, other)
   def - (other: UInt): UInt = this -% other
-  def -% (other: UInt): UInt = binop(UInt(this.width max other.width), SubModOp, other)
+  def -% (other: UInt): UInt = (this -& other) tail 1
   def * (other: UInt): UInt = binop(UInt(this.width + other.width), TimesOp, other)
   def * (other: SInt): SInt = other * this
   def / (other: UInt): UInt = binop(UInt(this.width), DivideOp, other)
@@ -410,13 +428,13 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
   /** add (default - no growth) operator */
   def + (other: SInt): SInt = this +% other
   /** add (no growth) operator */
-  def +% (other: SInt): SInt = binop(SInt(this.width max other.width), AddModOp, other)
+  def +% (other: SInt): SInt = (this +& other).tail(1).asSInt
   /** subtract (width +1) operator */
   def -& (other: SInt): SInt = binop(SInt((this.width max other.width) + 1), SubOp, other)
   /** subtract (default - no growth) operator */
   def - (other: SInt): SInt = this -% other
   /** subtract (no growth) operator */
-  def -% (other: SInt): SInt = binop(SInt(this.width max other.width), SubModOp, other)
+  def -% (other: SInt): SInt = (this -& other).tail(1).asSInt
   def * (other: SInt): SInt = binop(SInt(this.width + other.width), TimesOp, other)
   def * (other: UInt): SInt = binop(SInt(this.width + other.width), TimesOp, other)
   def / (other: SInt): SInt = binop(SInt(this.width), DivideOp, other)
-- 
cgit v1.2.3